STT-mram read operation method and read circuit of symmetrical reference cell type

Abstract

The invention discloses a reading operation method and a reading circuit of a symmetrical reference unit type, which adopt two resistance values ​​R L and R H The reference unit is used as the basis for data comparison. The structure combining positive and negative feedback effectively increases the readout range of the read circuit and improves the reliability of the read operation on the premise of ensuring the stability of the overall circuit. The Monte Carlo simulation results show that when the MTJ of the data branch is in a high-impedance state, the voltage detection node ranges of the data branch and the two reference branches are: 440.318~514.61mV, 445.649~506.16mV, 180.927~275.014mV ; When the MTJ of the data branch is in a low resistance state, the voltage detection node ranges of the data branch and the two reference branches are respectively: 271.142-389.693mV, 256.649-399.283mV, 444.124-512.517mV. The invention can greatly increase the readout range of the readout circuit on the premise that the readout current value is small, and can effectively improve the reliability of the readout operation.

Description

technical field [0001] The invention belongs to the field of circuit design of a novel nonvolatile magnetic random access memory (SpinTransfer Torque Magnetic Random Access Memory, STT-MRAM), and more specifically relates to a symmetrical reference cell type STT-MRAM Read operation method and symmetrical reference cell type read circuit. Background technique [0002] From the point of view of the continuous development of the memory, the problem of the memory wall has become the key to restricting the processor from improving performance and reducing power consumption. In the processor architecture, there is a Static Random Access Memory (SRAM) with a small scale or capacity but a high speed between the processor and the main memory Dynamic Random Access Memory (DRAM). Cache memory Cache. CPUs with increasingly faster processing speeds require larger-capacity caches to address data access pressures, and SRAMs face two important challenges: storage capacity and energy consu...

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Problems solved by technology

[0006] For the above defects or improvement needs of the prior art, the present invention provides a STT-MRAM read operation method of a symmetrical reference cell type and a read circuit of a symmetrical reference cell type, thereby solving the problem of limited read operation of the traditional STT-MRAM read operation method. Current and read operation reliability problems are highlighted, which hinders the technical problems of STT-MRAM integrated application in system chips

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