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An SOC chip system-level verification system and an SOC chip system-level verification method

A chip system and verification system technology, applied in CAD circuit design, special data processing applications, instruments, etc., can solve the problems of insufficient flexibility and low verification efficiency, simplify the work of maintaining code, speed up rapid convergence, and improve the overall The effect of work efficiency

Active Publication Date: 2019-04-26
上海芯钛信息科技有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] The present invention provides a SOC chip system-level verification method and system, which are used to overcome defects such as low verification efficiency caused by insufficient flexibility of CPU control in the simulation test process in the prior art, and improve the flexibility of CPU control in the simulation test process simplifies code maintenance and improves verification efficiency

Method used

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  • An SOC chip system-level verification system and an SOC chip system-level verification method
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  • An SOC chip system-level verification system and an SOC chip system-level verification method

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Embodiment 1

[0036] Please refer to figure 2 , the present invention provides a SOC chip system-level verification system, including a SOC chip 1 and a simulation platform 2;

[0037] The SOC chip 1 includes a CPU 11, a debugging interface 14 connected to the CPU 11, a module to be verified 12, and an excitation sending interface 15 connected to the module 12 to be verified by other design logic 13;

[0038] Described emulation platform 2 comprises control CPU model 21, incentive sending model 22 and result analysis model 23; Wherein:

[0039] The control CPU model 21 is connected with the module 12 to be verified by the debugging interface 14 according to the interface protocol; when the verification starts, receive the indication signal of the verification start and control the CPU11 to enter the debugging mode, and receive the verification end indication signal when the verification ends and Controlling the CPU 11 to exit the debugging mode, the CPU 11 acts in accordance with the inst...

Embodiment 2

[0051] Please refer to image 3 , for the concrete realization that this invention is applied to the application of I2C interface:

[0052] The verification environment mainly includes:

[0053] 1. The stimulus generating and sending component (stimulus sending model 22) is mainly connected to the corresponding pins of the SOC design (SOC chip 1) to be tested through the I2c_interface according to the I2C interface protocol, and the components of the test design can be sampled at the same time. Respond or return data.

[0054] 2. The control CPU component (control CPU model 21) is mainly connected to the corresponding controller of the SOC design to be tested through jtag_interface according to the jtag interface protocol, and the CPU enters the debug mode by accessing the cpu register. In this mode, the CPU enters the halt (pause) state, the behavior of the CPU is completely taken over by jtag.

[0055] 3. Other components (result analysis model 23) are mainly used for aut...

Embodiment 3

[0059] The embodiment of the present invention also provides a SOC chip system-level verification simulation platform, including the simulation platform in the SOC chip system-level verification system of any embodiment.

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Abstract

The invention discloses an SOC chip system-level verification system and method. The system comprises a simulation platform and an SOC chip. The chip comprises a CPU, a debugging interface, a module to be verified and an excitation sending interface. The simulation platform comprises a control CPU model which is connected with a module to be verified through a debugging interface according to an interface protocol; Receiving an indication signal of verification starting and controlling the CPU to enter a debugging mode, receiving an indication signal of verification ending and controlling theCPU to exit the debugging mode, and enabling the CPU to act according to an instruction for controlling the CPU model in the debugging mode; The excitation sending model is connected with the to-be-verified module through an excitation sending interface according to an interface protocol, and is used for generating excitation data, sending the excitation data to the to-be-verified module and collecting or receiving response data of the to-be-verified module; And the result analysis model is used for analyzing and judging the response data of the verification module, outputting a verification result and outputting an indication signal indicating that the verification is finished according to the verification result. According to the scheme, the problem of low verification efficiency causedby tedious and complex code maintenance is solved, code maintenance is simplified, and the verification efficiency is improved.

Description

technical field [0001] The invention relates to the technical field of integrated circuit design, in particular to a SOC (System On Chip, system on chip) chip system-level verification system and method. Background technique [0002] With the development of the integrated circuit industry, the presented SOC chips are becoming more and more complex, and the overall requirements for verification are also getting higher and higher. In the development cycle of chip design, the working time of verification accounts for about 80% of the entire cycle. , so it is very meaningful to study how to improve the efficiency of verification work under such a background. [0003] At present, the verification of SOC needs to write a driver program based on C language, compile the driver instruction program through a suitable compiler, and finally write it into the memory in the simulation platform for the CPU to fetch instructions and execute them. At the same time, the verification simulatio...

Claims

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Application Information

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IPC IPC(8): G06F17/50
CPCG06F30/398G06F30/367G06F30/39
Inventor 高攀冯华李澜涛林宗芳蒋晓倩李佐钟伟熊民权赵宗盛
Owner 上海芯钛信息科技有限公司
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