Two-dimensional layered material-based avalanche field-effect transistor and measurement device

Abstract

The invention discloses a two-dimensional layered material-based avalanche field-effect transistor and a measurement device. The transistor comprises an insulation layer, a metal electrode layer, a two-dimensional material thin film layer, a two-dimensional material thin film layer and a two-dimensional material thin film layer, wherein the metal electrode layer comprises a drain electrode layer,a source electrode layer and a gate electrode layer, the two-dimensional material thin film layer and the two-dimensional material thin film layer are laid on the insulation layer, the two-dimensionalmaterial thin film layer is arranged between lamination parts, the source electrode layer covers a non-stack part of the two-dimensional material thin film layer, the drain electrode layer covers a part above the stack parts or the non-stack part of the two-dimensional material thin film layer, and the gate electrode layer is connected with the insulation layer. The measurement device comprises atwo-dimensional layered material-based avalanche field-effect transistor, a voltage source and an ampere meter. By the transistor, the sub-threshold swing of the field-effect transistor is reduced tobe smaller than 1mV / dec, and low power consumption is achieved; and moreover, the device size is reduced, and the device stability is improved.

Description

technical field [0001] The invention relates to a transistor and a measuring device, in particular to an avalanche field effect transistor and a measuring device based on a two-dimensional layered material. Background technique [0002] The rapid development of information technology relies on the continuous increase in the number of transistors and the continuous reduction in transistor size. However, silicon-based transistors have encountered two fatal bottlenecks in further miniaturization. One is that shrinking device dimensions have caused the gate voltage to lose control of the transistor, preventing it from completely turning off the transistor. Another problem is that the power consumption cannot be reduced because the thermal emission model limits the subthreshold swing of the FET to less than 60mV / dec at room temperature. This limits the further reduction of the voltage of the transistor, and also limits the realization of low power consumption. In order to redu...

AI Technical Summary

Problems solved by technology

However, silicon-based transistors encounter two fatal bottlenecks in further miniaturization

One is that shrinking device size causes the gate voltage to lose control of the transistor, unable to completely turn off the transistor

Another problem is that the power consumption cannot be reduced, because the thermal emission model limits the subthreshold swing of the field effect transistor at room temperature to less than 60mV / dec

This limits the further reduction of the voltage of the transistor, which limits the realization of low power consumption

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