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configurable parallel BCH error correction coding method

An error correction coding and coding technology, applied in the field of data error correction, can solve problems such as low computing efficiency and inability to meet high-speed data processing

Inactive Publication Date: 2019-05-14
TIANJIN JINHANG COMP TECH RES INST
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  • Claims
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Problems solved by technology

[0012] The above method is simple and feasible, but it can only be calculated bit by bit, so the calculation efficiency is very low and cannot meet the requirements of high-speed data processing

Method used

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  • configurable parallel BCH error correction coding method

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Embodiment Construction

[0031] In order to make the purpose, content, and advantages of the present invention clearer, the specific implementation manners of the present invention will be described in further detail below in conjunction with the accompanying drawings and examples.

[0032] A configurable parallel BCH error correction coding method of the present invention includes: in order to improve computing efficiency and realize parallel computing, the following algorithm uses p as the data bit width for parallel computing. First, two settings are given: one is that the information bit k can be divisible by p, that is, kmodp=0; the other is that p is smaller than the check bit length r.

[0033] Firstly, the original information polynomial M(x) is divided into p groups in the following way to obtain:

[0034] M(x)=M 0 (x)+M 1 (x)+...+M p-1 (x),

[0035] in

[0036] Further calculations:

[0037]

[0038] in

[0039] Then, the encoding check digit S(x) can be expressed as:

[0040]...

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Abstract

The invention relates to a configurable parallel BCH error correction coding method, and the method comprises the steps: determining the coding configuration: an information bit k, a check bit r, a code word length n, an error correction bit t, and a primitive polynomial f (x); Calculating parameters: generating a polynomial g (x); Generating a polynomial matrix Tg, and verifying the calculation matrix Tg (p-1); Generating and calculating processing circuit. Performing coding calculation, including: inputting information bit data in parallel; Calculating check bit data; And judging whether theinput is finished or not, if so, outputting information bit data M (x), and if not, outputting check bit data S (x). According to the coding method, parallel input and output of data are realized, the time consumption of the processing flow is reduced in equal proportion, and the coding processing efficiency is remarkably improved.

Description

technical field [0001] The invention belongs to the field of data error correction, in particular to a parallel BCH error correction encoding method with configurable parameters and hardware implementation. Background technique [0002] BCH code is an encoding and decoding algorithm that can effectively correct data errors. Through encoding and calculation, the parity bit is added to the original information bit for data transmission. The receiver decodes the acquired data and corrects the error information when necessary. This algorithm It is often used to correct the bit errors in the channel transmission of data sending and receiving in the communication system, or the data error correction in the process of data writing and reading back in the data memory. BCH codes belong to linear block codes, which have strong error correction ability for randomly occurring multiple error bits, especially in short or medium code lengths, the performance is close to the theoretical val...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03M13/15
Inventor 周津何全
Owner TIANJIN JINHANG COMP TECH RES INST
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