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A high sustaining voltage esd device based on scr

An ESD device, high sustain voltage technology, applied in the field of electronic science and technology, to achieve the effect of improving robustness

Active Publication Date: 2021-01-22
UNIV OF ELECTRONICS SCI & TECH OF CHINA
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Therefore, the ESD device layout area, high sustain voltage and strong ESD robustness constitute a contradictory relationship that is difficult to compromise

Method used

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  • A high sustaining voltage esd device based on scr
  • A high sustaining voltage esd device based on scr
  • A high sustaining voltage esd device based on scr

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0028] like figure 2 As shown, the device structure of this embodiment includes: a P-type substrate 101, an NWELL region 201 located on the left side above the P-type substrate 101, a first N+ contact region 211 located above the inside of the NWELL region 201, and a first N+ contact region 211 located inside the NWELL region 201. The first P+ contact region 111 above; wherein, the P+ contact region 111 is located on the right side of the first N+ contact region 211; the PWELL region 102 located on the right side above the P-type substrate 101, and the first Zener located above the PWELL region 102 Implantation region 121, the second N+ contact region 212 located above the interior of the PWELL region 102, and the second P+ contact region 112 located above the interior of the PWELL region 102; wherein, the first Zener implant region 121 covers the second N+ contact region 212 with a size of D1, 0≤D1<total size of the second N+ contact region, the second P+ contact region 112 ...

Embodiment 2

[0034] like image 3 As shown, the difference between the device structure of this embodiment and Embodiment 1 is that there is an N+ floating region 213 tangent to the first P+ contact region 111 in the middle of the intersection of the NWELL region 201 and the PWELL region 102, and the N+ floating region 213 The distance between the right side and the first Zener injection region 121 is D2.

Embodiment 3

[0036] like Figure 4 As shown, the main difference between this embodiment and Embodiment 2 is that: P+ floating region 113 is provided on the upper surface of PWELL region 102, the left side of P+ floating region 113 coincides with the left side of the first Zener injection region 121, and the P+ floating region The right side of region 113 is tangent to the left side of second N+ contact region 212 .

[0037] Figure 11 It is the I-V characteristic diagram of the bias parameter D1 in Embodiment 1, where Conv.SCR is the IV curve obtained by the simulation of the traditional SCR device structure. By adjusting the distance D2 between the floating N+ region and the floating P+ region, the trigger voltage can be adjusted. As can be seen from the experimental results, as D1 increases, the I-V characteristics of the device of the present invention are close to the ESD protection device characteristics based on PNP. When D1=1 μm, the device No snapback feature.

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PUM

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Abstract

The present invention provides a high sustaining voltage ESD device based on SCR, comprising: P-type substrate, NWELL region, first N+ contact region, first P+ contact region, PWELL region, first Zener implant region, second N+ contact region, the second P+ contact region; the first Zener implanted region covers the second N+ contact region with a size of D1, and the second P+ contact region is located on the right side of the second N+ contact region; the first N+ contact region and the first P+ contact region pass through The metal anode is short-circuited to form a metal anode; the second N+ contact area and the second P+ contact area form a metal cathode through a metal short-circuit, and the present invention can control the Zener injection to cover the second N+ contact area distance D1 to adjust the maintenance voltage of the device. The trigger voltage is adjusted by controlling the distance D2 between the floating N+ region and the floating P+ region. The layout structure of the present invention significantly improves the robustness of the device without increasing the lateral area.

Description

technical field [0001] The invention belongs to the field of electronic science and technology, and mainly relates to the electrostatic discharge (ElectroStatic Discharge, referred to as ESD) protection technology on the integrated circuit chip, specifically relates to a class of high robustness and strong anti-latch (latch- up) capability, ESD protection device for high-voltage integrated circuits. Background technique [0002] ESD stands for Electrostatic Discharge, which is a common phenomenon in nature. ESD exists in every corner of people's daily life. But it is such a common electrical phenomenon that is a fatal threat to sophisticated integrated circuits. However, for chips that have been packaged, each power supply / input / output pin becomes a channel for pulse currents such as human body model (HBM), machine model (MM), and human body metal model (HMM). Strong ESD pulses will not only cause hard failure of the chip, but also induce various effects caused by imprope...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L27/02
Inventor 乔明齐钊何林蓉肖家木梁龙飞童成伟张发备张波
Owner UNIV OF ELECTRONICS SCI & TECH OF CHINA