A DDR clock path and a low-power-consumption duty ratio correction circuit thereof

Abstract

The invention discloses a DDR clock path and a low-power-consumption duty ratio correction circuit thereof. The circuit comprises a coupling circuit, an anti-phase transmission circuit and an output circuit which are sequentially connected between a clock input end and a clock output end, a straight-through circuit of which the input end and the output end are respectively connected with the clockinput end and the clock output end, and a feedback circuit connected between the output end and the input end of the anti-phase transmission circuit; The clock path comprises an RCV circuit, a low-power-consumption duty ratio correction circuit, a DLL circuit and a DCC circuit which are connected in sequence. The circuit can perform direct output through the straight-through circuit under the condition that the duty ratio requirement is met, and perform duty ratio adjustment through the reverse transmission circuit under the condition that the duty ratio requirement is not met, so that the transmission efficiency is greatly improved, the power consumption of the device is reduced, and the area of the device is also reduced; The DDR clock path setting method is short in link and fast in processing, and can effectively solve the problem that a clock in a DRAM clock system is lost on the clock path when the DDR clock path setting method is set in the DDR clock path.

Description

technical field [0001] The invention relates to a DRAM duty ratio correction circuit, in particular to a DDR clock path and a low power consumption duty ratio correction circuit. Background technique [0002] The traditional duty cycle correction circuit is mainly composed of DCC delay chain 1, DCC delay chain 2, phase detector, controller and clock synthesizer, etc., such as figure 1 shown. After clock 000 passes through DCC delay chain 1 and DCC delay chain 2, clock 360 is obtained. Clock 000 and clock 360 are compared in the phase detector, and the controller increases or decreases the length of the DCC delay chain according to the output of the phase detector until Clock 000 and Clock 360 are phase aligned. When the phases of the clock 000 and the clock 360 are aligned, the delay time of the clock 180 and the clock 000 is just half a clock period. Clock 000 and clock 180 are combined in the clock synthesizer to obtain the output clock, such as figure 2 shown. Becau...

AI Technical Summary

Problems solved by technology

Because it involves two delay chains and related matching circuits, when realizing duty cycle adjustment, it has high power consumption, large area, and complicated circuit; at the same time, it is easy to cause the loss of clock signal when it is used on the DDR clock path

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