Split-gate SONOS (Semiconductor Oxide Nitride Oxide Semiconductor) memory device

Abstract

The invention provides a split-gate SONOS (Semiconductor Oxide Nitride Oxide Semiconductor) memory device. The split-gate SONOS memory device comprises a gate oxide layer and a nitrogen oxide layer which are formed on a substrate, wherein a selection tube polysilicon gate, a top end oxide layer and an isolation layer are arranged on the gate oxide layer; a memory tube polysilicon gate is arrangedon the nitrogen oxide layer; the nitrogen oxide layer and one side of the memory tube polysilicon gate are close to the isolation layer; a memory tube P-type well is positioned below the selection tube polysilicon gate and the memory tube polysilicon gate; the substrate channel between the source end of the selection tube and the selection tube polysilicon gate is provided with a P-type boron injection region; and the channel of the P-type substrate below the memory tube polysilicon gate is provided with an N-type arsenic injection region. According to the invention, a single-side boron injection region of the selection tube and a source-end single-side arsenic or antimony injection region are formed, and boron in the boron injection region is diffused into a channel of the selection tubeto realize threshold voltage adjustment of the selection tube; an N-type arsenic injection region is formed through the threshold voltage adjustment of the memory tube; and finally, threshold voltageadjustment of the selection tube and threshold voltage adjustment of the memory tube device are not influenced mutually, the device performance is improved, and the manufacturing cost is reduced.

Description

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AI Technical Summary

Benefits of technology

The inventive technology allows for better control over how much charge can be stored on certain parts within one chip without compromising its overall functioning well. This results from injecting nitrogen gas (N_{2) during production processes that create silicon dioxide layers inside the chips's active area called gate oxides. By controllably distributing this dopant throughout these regions, it becomes possible to achieve specific desired properties such as lower leakage current and reduced power consumption compared with traditional methods like adding extra mask steps after fabrication.}

Problems solved by technology

This patented technical problem addressed in this patents relates to improving the efficiency and reliability of semiconductoreflectronic memories like FinFETS or MESCIs while reducing their size without sacrificially compromising data retention capabilities.

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