A time synchronization method for gateway communication data based on fpga+arm architecture
An ARM architecture, communication data technology, applied in electrical digital data processing, clocks driven by synchronous motors, electronic timers, etc., can solve problems affecting time information transmission, complex circuit structure, time transmission delay, etc. Time transmission, strong anti-interference ability, fast transmission effect
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[0045] After the system is started and running, the gateway communication module FPGA receives the IRIG-B time information of the 485 serial port, and parses out the BCD time information t at this time according to the B code frame format 1 : A year B day C hour D minute E second, by judging whether A year is a leap year, after converting B day into B1 month B2, convert all time information into hexadecimal t 1 ': A' year B1' month B2' day C' hour D' minute E' second, and perform CRC check on t1' and write it into the shared RAM area; when FPGA parses out t 1 After timing 410ms that is in the next second t 2 The rising edge of the quasi-second symbol outputs PPS 1 . If the FPGA parses the wrong time information, it will not output the PPS 1 second pulse.
[0046] PPS1 directly interrupts ARM, after ARM interrupts, confirm whether PPS1 is within the allowable range of time accuracy error, if so, update the time t' before ARM 0 +2s to time stamp the communication data, clear...
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