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Multi-valued electronic arithmetic device with numerous digits, grouping and reconfigurability, and method
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An arithmetic unit and a technology that can be grouped, applied to logic circuits with logic functions, instruments, calculations, etc., can solve problems such as large limitations
Active Publication Date: 2019-06-07
SHANGHAI UNIV +7
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Problems solved by technology
The technology described in this patent only involves optical arithmetic units, not electronic arithmetic units, and its arithmetic primitives can only complete the operation of one element in the logic operation truth table, which has relatively large limitations
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Embodiment 1
[0058] This embodiment describes the structure of a four-valued logic electronic operator represented by a two-digit binary symbol. The electronic arithmetic unit can have m bits, and the structure and working principle of each bit are the same, such as figure 2 . Therefore, this specification only describes the i-th bit in detail in conjunction with Fig. 2, i=0,1,...,m-1.
[0059] Each bit of the four-valued logic electronic operator of the embodiment of the present invention includes 4 column operators ( and ), a four-input OR gate consisting of two ( and ) composed of potential multipliers The difference between these 4 column operators is only the A signal selector and structure is different. in yes or no gate, The two input terminals can be connected to A arbitrarily i 1 (the high bit of the i-th line of the data line A) and A i 0 (the low bit of the i-th line of the data line A); It is an AND gate with a single input terminal, and the input te...
Embodiment 2
[0084] This embodiment describes the structure of a three-valued logic electronic operator represented by a two-digit binary symbol. The electronic arithmetic unit can have m bits, and the structure and working principle of each bit are the same, such as image 3 . Therefore, this specification only describes the i-th bit in detail in conjunction with Fig. 3, i=0,1,...,m-1.
[0085] In this embodiment, three symbols of 00, 01 and 10 of the two-bit binary symbol are selected to represent ternary data. When 11 and the other two symbols are selected to represent ternary data, the corresponding circuit only changes the A signal selector. and this change is already combining figure 1 It is described in detail in the general structure description of , so this different choice of symbols should not narrow the coverage of this embodiment.
[0086] Each bit of the three-valued logic electronic operator of the embodiment of the present invention comprises 3 column operators ( and )...
Embodiment 3
[0112] This embodiment describes the structure of a three-valued logic electronic operator represented by a one-bit three-valued symbol. The electronic arithmetic unit can have m bits, and the structure and working principle of each bit are the same, such as Figure 4 . Therefore, this manual only combines Figure 4 Describe its i-th bit in detail, i=0,1,...,m-1.
[0113] In this embodiment, three symbols 0, 1 and 2 are selected to represent ternary data, respectively representing three stable levels: V0 volts, V1 volts and V2 volts, and V0
[0114] For the detailed circuit structure and components of the i-th operator bit, see Figure 4 . It is characterized in that: the operator bit contains 3 column operators and and an amalgamator for the output signals of each column operator and signal combiner and the structure diagram of embodiment two ( image 3 ) comparison shows that: the present embodiment is c...
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Abstract
The invention discloses a multi-valued electronic arithmetic device with numerous digits, grouping and reconfigurability and a method. Each bit of the electronic arithmetic device comprises n column arithmetic devices and a potential superimposer, each column arithmetic device is structurally characterized in that a data input line A is connected with the input end of a signal selector A, and theoutput end of the signal selector A is connected with a work permitted device. The other input end of the work permitter is connected with the reconstruction latch, and the output end of the work permitter is also connected with the output effective device. The other input end of the output effective device is connected with the power supply Vcc, and the output end of the output effective device is connected with the output generator. The other input end of the output generator is connected with the reconstruction circuit, and the output end of the output generator is connected with the potential superimposer. Two input ends of the reconstruction circuit are respectively connected with the reconstruction latch and the B data input line. The input end of the reconstruction latch is connected with a reconstruction command line G. And the output end of the potential superimposer is a result signal of the arithmetic unit position. The value written into the reconfiguration latch determineswhether the logic operation rule and the operation of the operator bit are carried out or not.
Description
technical field [0001] The invention relates to the field of computer science and technology, in particular to a multi-valued electronic arithmetic unit with a large number of digits, which can be grouped and reconfigured, and its construction and use method. Background technique [0002] The current research on ternary optical computers has obtained a number of results, but the main technical points usually lie in optical arithmetic units, and there are no reports on electronic arithmetic units. [0003] There are two patents related to the embodiment of the present invention: [1] No-carry and no-borrow n-value arithmetic unit, Chinese patent: ZL200710041144.1, date of authorization: 2009-10-28. The main points of this invention are: 1. A general method for constructing a multi-valued arithmetic unit is disclosed, the main technology of which is implemented in an optical arithmetic unit, and does not involve how to construct an electronic arithmetic unit. 2. The core techn...
Claims
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