Static random access memory circuit structure for realizing Hamming distance calculation in memory

Abstract

The invention discloses a static random access memory circuit structure for realizing Hamming distance calculation in a memory. The circuit structure comprises a static random access memory (SRAM) array with N rows and N columns. An original code and an inverse code of a target binary data to be processed are stored in N columns and N bits of storage arrays of the SRAM array respectively, the N bits of binary data compared with the original code and the inverse code of the target binary data to be processed are stored in a word line signal WLL, and the N bits of binary data of the comparison data are stored in a word line signal WLR in an inverse code mode; bit line signals are reduced to VDD-Vx by bit line pulse modulation, preventing the stored data in the unit from overturning; and calculating the Hamming distance of the N columns through the sum of the BL and BLB discharge amounts of the bit line signals in each column, thereby calculating the Hamming distance of the N-bit binary data and the N-bit comparison data. The circuit is simple in structure, the operation efficiency and speed can be effectively improved, and energy consumed in the transmission process is reduced.

Description

technical field [0001] The invention relates to the technical field of integrated circuits, in particular to a static random access memory circuit structure for realizing Hamming distance calculation in memory. Background technique [0002] At present, with the rapid development of application fields such as machine learning, image recognition, and edge computing, these fields need to process massive amounts of data and require high computing energy efficiency. The traditional traditional von Neumann architecture separates the processor computing unit from the memory. The processor reads data from the memory when needed, and then writes it back to the memory after the processor has processed the data. Due to the rapid development of Moore's Law, the running speed of the memory is not synchronized with the speed of the processor, and the access speed of the memory is seriously lagging behind the computing speed of the processor. The performance of the memory has become an imp...

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Problems solved by technology

[0009] However, the scheme structure of the above-mentioned prior art is relatively complicated, a

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