Semi-super-junction lateral double-diffused metal oxide semiconductor field-effect transistor with stepped N-type heavily-doped buried layer

Abstract

The invention provides a semi-super-junction lateral double-diffused metal oxide semiconductor field-effect transistor with a stepped N-type heavily-doped buried layer. An N-type drift assisted regionis formed in a middle region of the upper portion of a P-type epitaxial layer; the left end of the N-type drift assisted region is adjacent to a P-type base region, and the right end of the N-type drift assisted region is adjacent to a semi-super-junction region; the stepped N-type heavily-doped buried layer is arranged in the P-type epitaxial layer; the distance W between the upper end of the relatively thin N-type heavily-doped buried layer and the semi-super-junction region meets the requirement that the P-type epitaxial layer above the relatively thin N-type heavily-doped buried layer iscompletely depleted; and the step height h of the stepped N-type heavily-doped buried layer is matched with the heavy doping concentration. While a substrate-assisted depletion effect is realized, electric field distribution of a drain end and a source end is adjusted to further optimize a contradiction relation between a breakdown voltage and specific on-resistance, thereby realizing high breakdown voltage and low specific on-resistance.

Description

technical field [0001] The invention relates to the technical field of semiconductor power devices, in particular to a semi-superjunction lateral double-diffused metal oxide semiconductor field effect transistor. Background technique [0002] The lateral power semiconductor device LDMOS (Lateral Double-diffused MOSFET) is the key technology of the high-voltage integrated circuit HVIC (High Voltage Integrated Circuit) and the power integrated circuit PIC (Power Integrated Circuit). Its main feature is that a relatively long lightly doped drift region is added between the base region and the drain region, and the doping type of the drift region is consistent with that of the drain region. By adding the drift region, it can share the breakdown voltage, improve the breakdown voltage of the LDMOS, make it achieve the optimization goal of low on-resistance, and minimize the conduction loss. Because of its high breakdown voltage, low on-resistance, and easy integration with low-vo...

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Problems solved by technology

[0004] However, for SJ-LDMOS, due to the substrate-assisted depletion of the N-type pillar region (or P-type pillar region), the P-type pillar region (or N-type pillar region) cannot be completely depleted when the device breaks down, breaking the N-type pillar region. The charge balance between the column area and the P-type column area reduces the lateral breakdown voltage of the SJ-LDMOS device

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