Multi-layer chip structure and connecting method

Abstract

Disclosed are multi-layer chip structures which can be connected with each other; integrated circuit chips with the same or different functions can be mutually connected through the bonding method ofa through silicon vias (TSV) and an implementation mode. The multi-layer chips are bonded through bonding of TSV to form cylinder metal interconnection; a top and bottom stacking mode is used betweenthe chips, or the chip flip chip stacking mode is used for realizing positioning alignment of the layers and the silicon through vias of the layers. Interconnection of the chips of different geometrical sizes in a stacking and bonding mode is carried out by metal bonding of the through silicon vias (TSV) in the fixed positions of the chips, and an auxiliary layer is added, so that the layers of chips can be continuously interconnected through the silicon through vias (TSV). The fixed-position silicon through vias (TSV) are vertically interconnected in a metalized mode and can be used as process positioning and alignment references, so that the interconnection and welding of the stacked chips are accurate, the process control is simple and convenient, the connection is reliable, the production of reasonable cost can be realized on a large scale, and electric connection between the layers can be simplified in a layer-crossing mode.

Description

technical field [0001] The invention relates to a semiconductor integrated circuit, in particular to a packaged internal multi-layer chip architecture and a connection method. Background technique [0002] The current integrated circuit three-dimensional chip technology and its implementation are: the direct connection between two chip stack layers or devices between at most three chip stack layers is vertically connected through through holes at any position. The location of the chip is determined according to the location of the required electrical connection device. This method is limited to vertical interconnection at a specific position of two-layer chips at most three-layer chips, whether it is a top-to-top or bottom-to-top stacking method. The location of the through hole is based on the location of the device. The positioning accuracy of the vertical interconnection method is not high, and it is difficult to accurately locate and align the upper and lower layer throu...

AI Technical Summary

Problems solved by technology

[0005] The purpose of the content of the present invention is to address the above-mentioned problems and defects existing in the current multi-layer chip 3D integrated circuit technology and provide an effective solution implementation method

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