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Cutting method of glass passivated silicon wafer

A technology of glass passivation and silicon wafers, applied in laser welding equipment, electrical components, circuits, etc., can solve problems such as high chip grain stress, affecting chip cutting pass rate and quality, front edge collapse, etc., to improve quality Effect

Inactive Publication Date: 2019-08-02
QIANGMAO ELECTRONICS WUXI CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, with the traditional method of mechanical splitting, the chip grains are subjected to a large stress of mechanical splitting, and the stress of the mechanical splitting cannot be uniform and stable, resulting in adverse phenomena such as side protrusions, side depressions, and front chipping of the chip grains, which affect The pass rate and quality of chip cutting may even lead to client failure

Method used

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  • Cutting method of glass passivated silicon wafer
  • Cutting method of glass passivated silicon wafer
  • Cutting method of glass passivated silicon wafer

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Experimental program
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Embodiment Construction

[0022] The present invention will be further described below in conjunction with the drawings.

[0023] A method for cutting glass passivated silicon wafers includes the following steps:

[0024] The first step is to manufacture normal glass passivated silicon wafers without the need to make positioning cuts. Refer to the invention patent for a laser cutting method for the back of glass passivated silicon wafers. The glass passivated silicon wafer device of the present invention is compared For the existing glass passivation silicon wafer device, there is no need to make a special positioning scribe line on the chip plating layer 1 on the back.

[0025] In the second step, the glass groove is used as a positioning reference, and the back laser half-cut through method is used for cutting. When the backside laser cutting of the glass passivated silicon wafer is performed, the groove 4 is used to place the glass passivated silicon wafer on a double-layer transparent glass sheet 9 with ...

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Abstract

The invention discloses a cutting method of a glass passivated silicon wafer, which comprises the steps of first, manufacturing a normal glass passivated silicon wafer without the need of manufacturing back positioning cutting channels; second, taking a glass groove as the positioning reference, and carrying out cutting in a back laser semi-cut-through manner; and third, carrying out scribing andfront cutting on chip grains. In the third step of carrying out scribing and front cutting on the chip grains, the back laser semi-cut-through wafer is pasted with a blue film on the back and put in ascribing and cutting machine, the glass groove of the wafer is taken as the positioning reference, front scribing and cutting are carried out by adopting a diamond cutter capable of cutting glass, and the semi-cut-through glass passivated silicon wafer is separated into single chip grains. The back of the wafer adopts the laser cutting mode, so that there are fewer problems such as edge breakageon the back of the wafer, there is no quality problems such as side surface bulge and side surface depression of the chip, and the problem of cutting deviation on the front and back sides does not occur.

Description

Technical field [0001] The invention relates to a method for cutting a wafer, belonging to the technical field of electronic component processing. Background technique [0002] At present, the structure of the existing glass passivation silicon wafer is shown as figure 1 , The back of the glass passivation silicon wafer has a chip nickel layer 1, the chip nickel layer 1 is closely attached to a layer of base silicon material 2, and the other side of the base silicon material 2 is provided with a PN junction 3. A plurality of trenches 4 are uniformly distributed on the front surface of the siliconized silicon wafer, and the trenches 4 are covered with a glass passivation layer 5 to provide surface passivation protection for the core structure PN junction 3 of the glass-passivated silicon wafer. There are spaced positioning cutting lanes 6 on the nickel layer 1 of the chip to facilitate position alignment during laser cutting on the back side. [0003] The applicant’s patent number ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/78B23K26/38
CPCB23K26/38H01L21/78
Inventor 方敏清
Owner QIANGMAO ELECTRONICS WUXI CO LTD