MDAC structure suitable for assembly line ADC

Abstract

The invention discloses an MDAC structure suitable for an assembly line ADC. The structure comprises a sampling input signal end VINP, a signal input end + / -VREF, a sampling signal input end VINN, anoperational amplifier OPAMP, a clock signal S1, a clock signal S2, sampling capacitors C1P-C8P, sampling capacitors C1N-C8N, a capacitor Cm, a capacitor Cn, a switch SW1, a switch SW2, a switch SW3, aswitch SW4, a switch SW5, a switch SW6, a switch SW7, a signal output end VOUTP and a signal output end VOUTN. The structure has beneficial effects are that the + VREF buffer and the-VREF buffer arealways consistent in load on the premise that the VCM buffer is not needed, the VCM voltage and a driver are not needed in the whole conversion process, and the dynamic performance of the driver is greatly improved.

Description

technical field [0001] The invention relates to the technical field of pipeline analog-to-digital converters, in particular to an MDAC structure suitable for pipeline ADCs. Background technique [0002] Pipeline analog-to-digital converter is a classic structure type of analog-to-digital converter. It can make a good compromise between power consumption, area, speed and accuracy, so it is widely used. High-precision pipeline analog-to-digital converter A multilevel structure is often used. In the traditional pipeline ADC (digital-to-analog converter) MDAC (residual gain amplifier circuit) structure such as figure 2 As shown, its working principle is as follows: [0003] 1. When the clock signal S1 is valid, MDAC is in the signal sampling stage: all sampling capacitors (C1P, C2P, ,,, C4P) and (C1N, C2N, ,,, C4N) respectively sample the input signal VINP and VINN, while C0 2. When the clock signal S2 is valid, the MDAC is in the margin amplification stage: the input termina...

AI Technical Summary

Problems solved by technology

[0006] It can be seen that when the input signal is constantly changing, the load of the driver of VCM, +VREF and -VREF is constantly changing, which puts strict requirements on the dynamic performance of the driver and increases the difficulty of driver design

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