Chip packaging process and chip packaging structure

A packaging structure and chip packaging technology, which is applied in the manufacture of electrical components, electrical solid devices, semiconductor/solid devices, etc., can solve problems such as large stress, increased heat dissipation, product reliability and operating cycle impact, and achieve stress tolerance Improvement of capacity, reduction of reliability risk, and improvement of heat dissipation efficiency

Pending Publication Date: 2019-09-17
BEIJING YANDONG MICROELECTRONICS
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0008] (1) The heat dissipation of the newly designed product increases, and it is difficult for the existing technology to deal with the efficiency of the heat dissipation itself to meet the product demand;
[0009] (2) The size of the internal chip of the newly designed product increases, so the area covered by the glue will increase, and the stress of thermal expansion and contraction of the product in the later use will also increase (the back of the chip and the heat dissipation cover);
[0010] To sum up, the direct conduction of heat dissipation of existing products and newly designed products depends on the physical contact heat dissipation cover on the back of the chip for heat dissipation. to influence

Method used

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  • Chip packaging process and chip packaging structure
  • Chip packaging process and chip packaging structure
  • Chip packaging process and chip packaging structure

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Embodiment Construction

[0046] In order to illustrate the present invention more clearly, the present invention will be further described below in conjunction with preferred embodiments and accompanying drawings. Similar parts in the figures are denoted by the same reference numerals. Those skilled in the art should understand that the content specifically described below is illustrative rather than restrictive, and should not limit the protection scope of the present invention.

[0047] In order to solve the technical problems proposed in the background technology, figure 1 Show a flow chart of a chip packaging process proposed by the first embodiment of the present invention, such as figure 1 As shown, the process includes the following steps:

[0048] S1. Flip-chip the chip 100 on the substrate;

[0049] S2. Baking the substrate on which the chip 100 is flip-mounted for the first time;

[0050] S3, cleaning the substrate on which the chip 100 is flip-mounted after the first baking;

[0051] S...

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PUM

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Abstract

The invention discloses a chip packaging process. The chip packaging process comprises the following steps of: baking a substrate inversely equipped with a chip for the first time; cleaning the substrate which is subjected to the first baking and is inversely provided with the chip; performing bottom filling on the cleaned substrate inversely equipped with the chip; baking the substrate which is inversely equipped with the chip and is subjected to the bottom filling for the second time; forming a plurality of grooves on the surface of one side, far away from the substrate, of the chip after backing for the second time; gluing the surface of one side, far away from the substrate, of the chip after grooving; attaching a cover plate on the surface of one side, far away from the substrate, of the chip after gluing; and baking the substrate which is inversely provided with the chip is attached to the cover plate for the third time. The chip packaging process can improve the heat dissipation efficiency of the chip.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a chip packaging process and a chip packaging structure. Background technique [0002] With the advancement of technology, the integration level of integrated circuit chips has been continuously improved, the number of I / O pins has increased sharply, and the power consumption has also increased accordingly, and the requirements for integrated circuit packaging have become more stringent. In order to meet the needs of development, BGA packaging technology began to appear and was applied to manufacturing. [0003] BGA (Ball Grid Array Package) technology is ball grid array packaging technology. Once this technology appeared, it became the best choice for high-density, high-performance, multi-pin packages such as CPUs, motherboard south bridge chips, and north bridge chips. Moreover, the technology adopts the controllable collapse chip welding method, which can improve its ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/48H01L21/56H01L23/31H01L23/367
CPCH01L23/3675H01L21/563H01L21/4871H01L23/3157
Inventor 戴建业
Owner BEIJING YANDONG MICROELECTRONICS
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