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A memory detection device combining bist and ecc in a system chip

A system chip and detection device technology, applied in static memory, instruments, etc., can solve the problems of system performance degradation and increased processing overhead

Active Publication Date: 2021-05-18
ZHEJIANG UNIV +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Rewriting data will increase the processing overhead, which will lead to a significant decrease in system performance

Method used

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  • A memory detection device combining bist and ecc in a system chip
  • A memory detection device combining bist and ecc in a system chip
  • A memory detection device combining bist and ecc in a system chip

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Embodiment Construction

[0034] The technical solution of the present invention will be further described below in conjunction with the accompanying drawings.

[0035] The memory detection device combining BIST and ECC proposed by the present invention is as follows: figure 1 shown. The whole device is composed of a BIST circuit module, a selector, a memory and an ECC module, and the ECC module includes an ECC memory, an error correction encoder and an error correction decoder. The BIST circuit module is used to receive external test control signals, initiate test operations, manufacture test vectors, test results, and give test result signals; the selector is used to select the ECC module, and the ECC module is used in combination by BIST in a multiplexed manner. The architecture of the system is reconfigurable.

[0036] When the ECC module detects a problem, it cannot be used. At this time, BIST cannot reuse the ECC module, and the selector will not select the ECC module; figure 2 The shown ECC ...

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PUM

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Abstract

The invention provides a device for detecting memory of an ECC module in a BIST multiplexing system chip, which belongs to the field of memory detection. The device includes a BIST circuit module, an ECC memory, a memory, an error correction encoder, and an error correction decoder. When the ECC module has no errors, BIST can choose to reuse the ECC module. The device proposed by the invention detects it by reading and writing data to the memory. During this process, when a bit error occurs, it will be corrected by the ECC error correction decoder module, no error will be detected at the BIST detection end, and the detection result signal given is pass, which means that the area is still available of. When there are more than two-bit errors, it will be considered to be truly wrong, and a fail signal will be reported. The device improves the yield rate of the memory during detection.

Description

technical field [0001] The invention relates to the field of built-in self-test of memory, in particular to a memory detection device combining BIST and ECC in a system chip. Background technique [0002] Nowadays, semiconductor manufacturers mostly focus on the performance of storage array technology in terms of capacity, process technology, and quality. System on chip (soc, System on Chip), also known as system on chip, is to integrate a complete system on a single chip. System chips are mainly used in embedded systems, mobile devices, personal computers and other fields. At the same time, embedded memory is an important part of soc, and its performance index and reliability directly determine the performance of soc. The stability of embedded memories is becoming more and more important in the design and test world. In microprocessors and ASICs, large-scale SRAM (Static Random-Access Memory, Static Random-Access Memory) arrays, which are widely used as cache memory, occ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G11C29/42G11C29/44
CPCG11C29/42G11C29/44G11C2029/4402
Inventor 黄凯郑昌立余慜修思文
Owner ZHEJIANG UNIV