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Test chip marking method and chip yield improvement method

A marking method and chip technology, used in semiconductor/solid-state device testing/measurement, electrical components, circuits, etc., can solve problems such as yield decline, reduce losses, reduce packaging costs, and improve recognition.

Active Publication Date: 2019-10-08
NINGBO CHIPEX SEMICON
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

For the wafer-level packaging of such large-size chips (chip size is generally > 3mm*3mm), even a small chip loss will bring a large yield drop, so yield improvement has become an important issue

Method used

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  • Test chip marking method and chip yield improvement method
  • Test chip marking method and chip yield improvement method
  • Test chip marking method and chip yield improvement method

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0043] Wafer-level packaging (WLCSP) is to complete the packaging on the entire wafer and then cut it. This packaging method can obtain a large number of finished chips at one time, and some high-end products have relatively large chip sizes due to their high integration (chip The size is generally greater than 3mm*3mm), for such a large-sized chip using wafer-level packaging, even a small chip loss will bring a large drop in yield, in order to verify the quality of the product, it will be in the process of chip packaging Various performance tests are carried out in the process, so the necessary performance test and yield control are research hotspots.

[0044] An embodiment of the present specification provides a test chip marking method for rapidly determining the position of the test chip during the chip packaging process.

[0045] It should be noted that the test chip marking method provided in this embodiment is not only applicable to the wafer-level packaging process of ...

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PUM

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Abstract

The invention discloses a test chip marking method. The method comprises steps: a plurality of chip units are formed in a wafer, and the position of a test chip is determined, wherein the test chip isa chip in a wafer invalid area and / or a chip in a wafer light sheet area; the test chip is coated with a photoresist and a lithography plate and the wafer are arranged oppositely; the chip is exposedthrough the lithography plate; developing processing is carried out, the photoresist in a recognition pattern area and an electroplating opening area of the test chip is developed off, and the photoresist in the remaining areas coats the chip surface; and electroplating processing is carried out, an electroplating material fills the test mark area, and a test mark is formed. The invention also discloses a chip yield improvement method. Through function test on the chip marked by the above test chip marking method to complete product quality detection, the loss of the function chip is reduced,the packaging yield is improved, the packaging cost of a single chip is reduced, and the product competitiveness is improved.

Description

technical field [0001] The invention relates to the technical field of semiconductor chips, in particular to a method for marking test chips and a method for improving chip yield. Background technique [0002] Wafer Level Packaging (WLCSP) adopts the wafer operation mode in the integrated circuit chip manufacturing plant, that is, after the packaging is completed on the entire wafer and then cut, a large number of finished chips can be obtained at one time. Compared with traditional packaging, it has the advantages of high packaging efficiency, light, thin, short, and small chip size after packaging, high I / O density, and good electrical connection performance. It is the development trend of advanced packaging. [0003] Among them, some high-end products have a large single chip size due to their high integration. For the wafer-level packaging of such large-size chips (chip size is generally >3mm*3mm), even a small chip loss will bring a large yield drop, so yield improv...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/66
CPCH01L22/10H01L22/20Y02P80/30
Inventor 李春阳方梁洪钟志明任超彭祎
Owner NINGBO CHIPEX SEMICON