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Method and device for determining optimal value of chip drive EQ value

A technology for determining methods and optimal values, applied in the field of signal simulation, can solve problems affecting product development progress and investment in manpower and test resources, increasing test workload, and small test margins for high-speed link signals. Achieve the effect of improving precision and product development and design quality, reducing workload and resource investment

Active Publication Date: 2019-10-25
SUZHOU LANGCHAO INTELLIGENT TECH CO LTD
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  • Summary
  • Abstract
  • Description
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  • Application Information

AI Technical Summary

Problems solved by technology

[0004] Using the existing simulation method, although the signal transmission quality of high-speed complex links can be evaluated, the chip driver EQ value determined by the simulation simulation is not optimal because the impedance deviation caused by PCB board processing is not considered in the simulation simulation. Therefore, when the post-test is introduced, it is found that there is a problem that the high-speed link signal test margin is too small. Therefore, it is necessary to select the optimal value by means of EQ variable scanning through actual measurement, thus greatly increasing the test work. Affected the development progress of the product and the input of manpower and testing resources

Method used

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  • Method and device for determining optimal value of chip drive EQ value
  • Method and device for determining optimal value of chip drive EQ value
  • Method and device for determining optimal value of chip drive EQ value

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Experimental program
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Effect test

Embodiment 1

[0036] Such as figure 1 As shown, a method for determining the optimal value of a chip-driven EQ value comprises the following steps:

[0037] S1. Perform chip EQ numerical scan on the link in combination with typical combinations of target impedances.

[0038] S2. Obtain all the EQ value scan results, and output the EQ value corresponding to the highest amplitude point of the simulated eye diagram result as the optimal value.

Embodiment 2

[0040] Such as figure 2 As shown, a method for determining the optimal value of a chip-driven EQ value comprises the following steps:

[0041] S1. Determine the upper and lower limit indicators of the target impedance control, determine the upper limit value of the impedance, the lower limit value of the impedance and the typical channel combination mode of the target impedance.

[0042] S2. Using all the EQ values ​​of the chip to simulate typical channel combinations.

[0043] S3. Output the combination of all simulated eye diagram result values ​​and their corresponding EQ values, and generate a schematic diagram of EQ values ​​corresponding to eye diagram amplitude changes.

[0044] S4. After the eye pattern results of the five channel combination simulations corresponding to the selected EQ values ​​are added and averaged, a group of EQ values ​​corresponding to the largest average value is the relatively best selected value.

Embodiment 3

[0046] For the EQ value of the current technology chip, the early method is to only simulate the typical impedance channel, and then use the simulation software to output an EQ value, which is designed and developed for the current Server motherboard. Transmission quality on the link, start to import high-speed signal simulation flow chart, as attached image 3 As shown, this method can be used to evaluate the quality of high-speed signal transmission, and at the same time can determine a set of chip EQ values, and use this value for board proofing testing. This value can meet the requirements of the typical channel, but when the channel impedance changes, its EQ value is not the best choice.

[0047] If the simulation evaluation is carried out with the existing scheme, the EQ value of the chip driver determined by the simulation will find that the test margin of the high-speed signal is too small during the board test. The value of merit, therefore, greatly increases the wor...

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Abstract

The invention discloses a method for determining an optimal value of a chip drive EQ value. The method comprises the following steps: performing chip EQ value scanning on a link in combination with atarget impedance typical combination; and obtaining all EQ numerical value scanning results, and outputting the corresponding EQ numerical value under the highest amplitude point of the simulated eyepattern result as the optimal value. The invention further provides a device for determining the optimal value of the EQ value of the chip driver. According to the invention, the high-speed link signal transmission quality risk is ensured to be controllable; the optimal EQ value of the chip driver is found out, and the EQ value can be effectively compatible with the influence of the signal test onthe impedance change of the high-speed link, so that the test workload and the resource investment are reduced, and the signal simulation evaluation precision and the product development and design quality are improved.

Description

technical field [0001] The invention relates to the technical field of signal simulation, in particular to a method and a device for determining an optimal value of a chip drive EQ value. Background technique [0002] In the current high-speed server motherboard design, with the increase of high-speed signal rate, various types of buses such as PCIE4.0 signal 16.0Gbps and SAS4.0 signal 24.0Gbps have begun to be introduced into product development and design. It poses challenges to the signal transmission quality of high-speed links with long-distance multi-card cascading. Therefore, in order to ensure the quality of high-speed signal transmission, signal simulation methods are usually introduced in the early stage of project development and design, so as to predict the signal quality of the entire interconnection transmission link in advance, and optimize the design points of high-risk links Adjustments are then simulated to evaluate the quality of improvement. Although th...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F17/50
CPCG06F30/39G06F30/367Y02E60/00
Inventor 武宁
Owner SUZHOU LANGCHAO INTELLIGENT TECH CO LTD