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A method and device for determining the optimal value of chip drive eq value

A technology to determine the method and optimal value, applied in the field of signal simulation and simulation, can solve the problems of increasing the test workload, affecting the product development progress and the investment of manpower and test resources, and not considering the PCB board impedance deviation, etc., to achieve The effects of reducing workload and resource investment, improving precision and quality of product development and design

Active Publication Date: 2022-07-08
INSPUR SUZHOU INTELLIGENT TECH CO LTD
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] Using the existing simulation method, although the signal transmission quality of high-speed complex links can be evaluated, the chip driver EQ value determined by the simulation simulation is not optimal because the impedance deviation caused by PCB board processing is not considered in the simulation simulation. Therefore, when the post-test is introduced, it is found that there is a problem that the high-speed link signal test margin is too small. Therefore, it is necessary to select the optimal value by means of EQ variable scanning through actual measurement, thus greatly increasing the test work. Affected the development progress of the product and the input of manpower and testing resources

Method used

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  • A method and device for determining the optimal value of chip drive eq value
  • A method and device for determining the optimal value of chip drive eq value
  • A method and device for determining the optimal value of chip drive eq value

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Experimental program
Comparison scheme
Effect test

Embodiment 1

[0036] like figure 1 As shown, a method for determining an optimal value of a chip-driven EQ value includes the following steps:

[0037] S1. Perform a chip EQ numerical scan on the link in combination with a typical combination of target impedances.

[0038] S2. Obtain the scanning results of all EQ values, and output the EQ value corresponding to the highest amplitude point of the simulated eye diagram result as the optimal value.

Embodiment 2

[0040] like figure 2 As shown, a method for determining an optimal value of a chip-driven EQ value includes the following steps:

[0041] S1. Determine the upper and lower limit indicators of the target impedance control, and determine the impedance upper limit value, the impedance lower limit value and the typical channel combination mode of the target impedance.

[0042] S2. Use all the EQ values ​​of the chip to simulate the typical channel combination.

[0043] S3. Output all the simulated eye diagram result values ​​and the combination of their corresponding EQ values ​​to generate a schematic diagram of the variation of the eye diagram amplitudes corresponding to the EQ values.

[0044] S4. After selecting the EQ value corresponding to the eye diagram results of the five-channel combination simulation, after adding and averaging, a group of EQ values ​​corresponding to the maximum mean value is a relatively optimal selection value.

Embodiment 3

[0046] According to the EQ value of the current technology chip, the early method is to use the simulation software to output an EQ value after only simulating the typical impedance channel. For the design and development of the current server motherboard, due to the improvement of the signal routing rate, in order to ensure that the high-speed signal is in the long distance. The transmission quality on the link, start to import the high-speed signal simulation flow chart, as attached image 3 As shown, this method can be used to evaluate the quality of high-speed signal transmission, and at the same time, a set of chip EQ values ​​can be determined, and this value can be used for board proofing testing. This value can meet the requirements of the typical channel, but when the channel impedance changes, its EQ value is not the best choice.

[0047] If the simulation evaluation is carried out with the existing scheme, the chip-driven EQ value determined by the simulation will f...

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Abstract

The invention discloses a method for determining an optimal value of a chip-driven EQ value, which comprises the following steps: performing a numerical scan of the chip EQ on a link in combination with a typical combination of target impedance; acquiring all the EQ numerical scan results, and outputting the highest amplitude point of the simulated eye diagram result The corresponding EQ value below is the optimal value. The invention also provides a device for determining the optimal value of the chip-driven EQ value. The invention can find out the optimal chip driving EQ value under the premise of ensuring the controllable risk of high-speed link signal transmission quality, and the use of this value can effectively be compatible with the signal test is the influence of the high-speed link impedance change, thereby reducing the need for The test workload and resource investment have improved the accuracy of signal simulation evaluation and the quality of product development and design.

Description

technical field [0001] The invention relates to the technical field of signal simulation, in particular to a method and a device for determining an optimal value of a chip-driven EQ value. Background technique [0002] In the current high-speed server motherboard design, with the increase of high-speed signal rate, various types of buses such as PCIE4.0 signal 16.0Gbps and SAS4.0 signal 24.0Gbps rate have been introduced into product development and design. It brings challenges to the signal transmission quality of high-speed links with long-distance multi-board cascading. Therefore, in order to ensure the quality of high-speed signal transmission, the method of signal simulation is usually introduced in the early R&D and design stage of the project, so as to estimate the signal quality of the entire interconnection transmission link in advance, and optimize the design point of the high-risk link. After adjustment, simulation evaluation improves the quality. Although this ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F30/398G06F115/12
CPCG06F30/39G06F30/367Y02E60/00
Inventor 武宁
Owner INSPUR SUZHOU INTELLIGENT TECH CO LTD