Device for improving testing rate of DDR device
A test rate and device technology, applied in the direction of instruments, static memory, etc., can solve the problems that DDR devices cannot be reduced in frequency, and the ATE data rate cannot meet the requirements of the main clock 400MHzDDR device, etc., to achieve the effect of increasing the test rate
Inactive Publication Date: 2019-10-25
CASIC DEFENSE TECH RES & TEST CENT
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Problems solved by technology
[0002] Due to the limitation of the test rate of the integrated circuit automatic test system (ATE), for the double-rate synchronous dynamic random access memory (DDR device) with a clock frequency of 400MHZ, the ATE data rate cannot meet the requirements of the main clock 400MHz DDR device
At the same time, since the DDR device cannot be tested by reducing the frequency, it is necessary to increase the test frequency of the ATE automatic test system
Method used
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[0018] In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be described in further detail below in conjunction with specific embodiments and with reference to the accompanying drawings.
[0019] It should be noted that all expressions using "first" and "second" in the embodiments of the present invention are to distinguish two entities with the same name but different parameters or parameters that are not the same, see "first" and "second" It is only for the convenience of expression, and should not be construed as a limitation on the embodiments of the present invention, which will not be described one by one in the subsequent embodiments.
[0020] refer to figure 1 As shown, it is a schematic structural diagram of a device for increasing the test rate of a DDR device according to an embodiment of the present invention. The device for testing the speed of a DDR device includes a software unit 101 , a har...
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The invention discloses a device for improving the test rate of a DDR device, and the device is characterized in that the device comprises a software unit, a hardware unit, and a switching circuit; the software unit is used for defining a plurality of driving edge characteristics according to a system signal, doubling the clock frequencies of a first to-be-written control signal, a data signal andan address signal to obtain a second to-be-written control signal, the data signal and the address signal, and inputting the second to-be-written control signal, the data signal and the address signal into the hardware unit; the hardware unit is used for doubling the clock frequency of the second to-be-written control signal, the data signal and the address signal to obtain a third to-be-writtencontrol signal, the data signal and the address signal, and inputting the third to-be-written control signal, the data signal and the address signal into the switching circuit; the switching circuit is used for writing the third to-be-written control signal, the data signal and the address signal into a DDR device; and the DDR device response data signal is output to a test system through the switching circuit.
Description
technical field [0001] The invention relates to the field of component testing, in particular to a double-rate synchronous dynamic random access memory test. Background technique [0002] Due to the limitation of the test rate of the integrated circuit automatic test system (ATE), for the double-rate synchronous dynamic random access memory (DDR device) with a clock frequency of 400MHZ, the ATE data rate cannot meet the requirements of the main clock 400MHz DDR device. At the same time, because the DDR device cannot be tested by reducing the frequency, it is necessary to increase the test frequency of the ATE automatic test system. Contents of the invention [0003] In view of this, the purpose of the present invention is to propose a combination of software and hardware to improve the ATE test rate, the clock frequency is doubled by hardware, and the clock frequency is doubled by software, from 100MHz to 400MHz. Meet the test rate of DDR devices. [0004] Based on the a...
Claims
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Login to View More IPC IPC(8): G11C29/56
CPCG11C29/56
Inventor 石雪梅
Owner CASIC DEFENSE TECH RES & TEST CENT