A Configurable General Convolutional Neural Network Accelerator

A convolutional neural network and accelerator technology, which is applied in the field of general convolutional neural network accelerators, can solve problems such as inability to adapt to changing neural network structure application requirements, and unsatisfactory network structure acceleration effects.

Active Publication Date: 2021-07-06
SOUTHEAST UNIV
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Problems solved by technology

[0006] The purpose of the present invention is to address the deficiencies of the above-mentioned background technology and provide a configurable general-purpose convolutional neural network accelerator. By configuring network parameters, the acceleration of convolutional neural network structures of various scales is realized, and neural networks with different structures Using different data multiplexing modes and highly parallelized processing units to obtain high computing throughput while using less resources, it solves the problem that existing hardware accelerators cannot adapt to the application requirements of changing neural network structures. The technical problem that the hardware accelerator is not ideal for the accelerated effect of the changing network structure

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  • A Configurable General Convolutional Neural Network Accelerator
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  • A Configurable General Convolutional Neural Network Accelerator

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[0022] The technical solution of the invention will be described in detail below in conjunction with the accompanying drawings.

[0023] The configurable general-purpose convolutional neural network accelerator designed by the present invention is as figure 1 As shown, the size of the two PE arrays is 14*16, the size of the convolution kernel is 3*3, the step size of the convolution kernel is 1, the size of the input feature map is 15*15 (after adding padding), and a single batch of input channels The number is 14, the number of output channels in a single batch is 32, and the data multiplexing mode is output multiplexing as an example to describe its working method in detail.

[0024] After the accelerator in the waiting state receives the start signal. The accelerator reads the network parameters from the external memory through the bus interface, updates the network parameter register, and determines the data reuse mode and the switching sequence of the working state accor...

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Abstract

The invention discloses a configurable universal convolutional neural network accelerator, which belongs to the technical field of calculation, calculation and counting. The accelerator includes: a PE array, a state controller, a function module, a weight buffer, a feature map buffer, an output buffer and a register stack, and the state controller includes a network parameter register and a working state controller. By configuring the network parameter registers, excellent acceleration effects can be achieved for networks of different scales. The working state controller controls the switching of the working state of the accelerator and sends control signals to other modules. The weight buffer, feature map buffer and output buffer are all composed of multiple data sub-buffers, which are used to store weight data, feature map data and calculation results respectively. The invention can configure appropriate data reuse mode, array size and number of sub-buffers according to different network characteristics, and has good versatility, low power consumption and high throughput.

Description

technical field [0001] The invention discloses a configurable universal convolutional neural network accelerator, which belongs to the technical field of calculation, calculation and counting. Background technique [0002] In recent years, deep neural networks have developed faster and been widely used, and have achieved remarkable results in text recognition, image recognition, target tracking, face detection and recognition and other application fields. The scale of the deep neural network continues to increase as the application scenarios become more complex, and a large number of parameters need to be stored and calculated. Therefore, how to accelerate and implement large-scale deep neural networks on hardware has become an important issue in the field of machine learning. [0003] GPU (Graphic Processing Unit, graphics processing unit) and multi-core CPU (Central Processing Unit, central processing unit) are commonly used devices to accelerate large-scale deep neural n...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06N3/04G06N3/063G06T1/20G06T1/60
CPCG06N3/063G06T1/20G06T1/60G06N3/045
Inventor 陆生礼庞伟舒程昊刘昊范雪梅苏晶晶
Owner SOUTHEAST UNIV
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