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MapReduce-based K-means clustering algorithm FPGA acceleration system

A k-means clustering and accelerating system technology, applied in computing, computer components, multi-programming devices, etc., can solve the problems of high computational complexity, slow speed, and large algorithm time overhead, and achieve low power, high efficiency Real-time, low-cost effects

Inactive Publication Date: 2017-11-21
HUAZHONG UNIV OF SCI & TECH
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Problems solved by technology

[0004] The present invention provides a K-means clustering algorithm FPGA acceleration system based on MapReduce under a large amount of data. Expensive bugs for faster computational processing

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  • MapReduce-based K-means clustering algorithm FPGA acceleration system
  • MapReduce-based K-means clustering algorithm FPGA acceleration system
  • MapReduce-based K-means clustering algorithm FPGA acceleration system

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Embodiment Construction

[0045] The present invention will be described in further detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present invention, not to limit the present invention.

[0046] When the K-means clustering algorithm is calculated and processed under the native MapReduce computing framework, all calculation stages of the K-means clustering algorithm are performed on a general-purpose processor, which has high time complexity and limited processing capacity. The invention is applied to the extended MapReduce computing framework, and aims at accelerating the processing of the K-means clustering algorithm. Based on the original MapReduce computing framework, the expanded MapReduce computing framework uses FPGA-based hardware acceleration system as a coprocessor to achieve high-performance computing, and migrates the CPU-intensive computing process in the K-means cl...

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Abstract

The invention provides a MapReduce-based K-means clustering algorithm FPGA acceleration system. The acceleration system mainly comprises a Map task data receiving and transmitting subsystem, a Map task acceleration subsystem, a Reduce task data receiving and transmitting subsystem and a Reduce task acceleration subsystem, wherein the Map task data receiving and transmitting subsystem transmits corresponding data from a PCIe terminal to the Map task acceleration subsystem and transmits a final calculation result of the Map task acceleration subsystem back to the PCIe terminal; and the Reduce task data receiving and transmitting subsystem transmits corresponding data from the PCIe terminal to the Reduce task acceleration subsystem and transmits a final calculation result of the Reduce task acceleration subsystem back to the PCIe terminal. According to the acceleration system, a time consumption calculation process needing to be performed is separated out of an upper layer, a special hardware system is adopted to perform corresponding calculation, and assembly line design and a concurrent processing method are adopted for all modules in the system, so that operation processing speed is greatly increased.

Description

technical field [0001] The invention belongs to a complex algorithm hardware acceleration system, in particular to a MapReduce-based K-means clustering algorithm FPGA acceleration system under a large amount of data. Background technique [0002] With the advent of the era of big data, the application of big data has increasingly demonstrated its advantages, and the fields it occupies are becoming larger and larger; however, the era of big data still faces some problems that need to be solved urgently, such as large data volume and value density. Low processing speed, high timing requirements, etc., so machine learning and data mining technologies are increasingly gaining attention in the computing field. [0003] Cluster analysis is an important content in data mining, and it is playing an increasingly important role in the fields of industry, commerce and scientific research. The K-means algorithm belongs to a basic division method in cluster analysis, and the error sum o...

Claims

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Application Information

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IPC IPC(8): G06F9/54G06F13/40G06K9/62
CPCG06F9/546G06F13/4027G06F18/23213
Inventor 李开曹计昌邹复好阳美玲黄浩
Owner HUAZHONG UNIV OF SCI & TECH
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