Method for forming a semiconductor device
A semiconductor and device technology, applied in the field of forming semiconductor devices, can solve the problems of limiting the number of solder balls, tin short circuit, quantity limitation, etc.
Active Publication Date: 2019-10-29
TAIWAN SEMICON MFG CO LTD
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- Description
- Claims
- Application Information
AI Technical Summary
Problems solved by technology
Due to the limited area of the die, the number of I / O pads is limited due to the limitation of the pitch of the I / O pads
Furthermore, with the fixed ball size requirement, the solder balls must be of a specific size, which in turn limits the number of solder balls that can be packaged on the surface of the die
Method used
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[0014] The following disclosure provides many different embodiments, or, for example, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are examples only and are not meant to be limiting. For example, forming a first component over or on a second component as described below may include embodiments where the first and second components are formed in direct contact, and may also include that additional components may be formed between the first and second components such that Embodiments in which the first part and the second part are not in direct contact. Additionally, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for brevity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.
[0015] In addition, spatially relative ...
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The embodiment of the present invention provides a method for forming a semiconductor device. The method includes forming a metal seed layer on a dielectric layer, and forming a patterned mask over the metal seed layer. An opening in the patterned mask is over a first portion of the dielectric layer, and the patterned mask overlaps a second portion of the dielectric layer. The method further includes plating a metal region in the opening, removing the patterned mask to expose portions of the metal seed layer, etching the exposed portions of the metal seed layer, performing a plasma treatment on a surface of the second portion of the dielectric layer, and performing an etching process on the surface of the second portion of the dielectric layer.
Description
technical field [0001] The present invention relates to the field of semiconductors, and more particularly, to methods of forming semiconductor devices. Background technique [0002] As semiconductor technology evolves, semiconductor chips / die become smaller and smaller. At the same time, more functions need to be integrated into the semiconductor die. Accordingly, semiconductor dies are required to have an increasing number of I / O pads packed into smaller areas, and the density of I / O pads increases rapidly over time. As a result, packaging of semiconductor dies becomes more difficult, which adversely affects the field of packaging. [0003] Conventional packaging techniques can be divided into two categories. In the first category, the dies on the wafer are packaged before being diced. This packaging technique has several advantageous features, such as greater throughput and lower cost. Additionally, less underfill or molding compound is required. However, this packa...
Claims
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IPC IPC(8): H01L21/48
CPCH01L21/4846H01L21/4853H01L21/568H01L21/6835H01L2221/68359H01L2221/68372H01L23/3128H01L23/295H01L2221/68381H01L2224/18H01L24/19H01L24/20H01L2224/82005H01L24/24H01L24/82H01L2224/24137H01L2224/12105H01L2224/04105H01L2224/83191H01L2224/27436H01L24/27H01L24/29H01L2224/2919H01L24/83H01L2224/82106H01L2224/82101H01L2224/73267H01L2224/92244H01L2224/1147H01L2224/11334H01L2224/11849H01L24/48H01L2224/48145H01L2224/32225H01L24/73H01L24/92H01L24/11H01L2224/131H01L2224/13147H01L2224/1146H01L2924/00014H01L2924/0001H01L2924/014H01L21/76811H01L21/76816H01L21/3065H01L21/02315H01L21/30604H01L21/76805H01L21/563H01L23/485H01L21/481H01L21/76871H01L21/32139H01L21/565H01L21/76856H01L23/3107H01L2224/02379H01L23/53238H01L24/09H01L24/14H01L24/17H01L24/32H01L23/5226
Inventor 谢昀蓁蔡惠榕郭宏瑞余振华
Owner TAIWAN SEMICON MFG CO LTD