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Program, information processing device, and information processing method

A technology for information processing equipment and processors, which is used in electrical digital data processing, special data processing applications, and digital data processing components, etc. It can solve the problems of delay in development completion schedule, lack of product introduction time, etc., and reduce simulation time. Effect

Pending Publication Date: 2019-11-22
RENESAS ELECTRONICS CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In this case, development needs to be done again from the beginning of the V model, resulting in a delay in the development completion schedule and a lack of product introduction time

Method used

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  • Program, information processing device, and information processing method
  • Program, information processing device, and information processing method
  • Program, information processing device, and information processing method

Examples

Experimental program
Comparison scheme
Effect test

no. 1 example

[0049]

[0050] image 3 is a block diagram for showing an example of the functional configuration of the improved program 116A according to the first embodiment. As a main functional configuration realized by executing the improved program 116A, the information processing apparatus 100 includes a data acquisition unit 31A, a clock frequency determination unit 32A, and a conversion ratio setting unit 35A. Although improved program 116A corresponds to figure 1 An improved program 116 is shown, but with an additional "A" appended for convenience to distinguish it from other embodiments. This also applies to the second and third embodiments.

[0051] In addition, the model 20 loaded to the main storage device 110 includes an input block 21 , conversion blocks 22 and 24 , an operation block 23 , and an output block 25 . Although Model 20 corresponds to figure 1 The model 114 is shown, but for simplicity of explanation, a case where one input block, one operation block, and...

no. 2 example

[0086] In the second embodiment, a configuration will be described in which the clock frequency of each block is determined while confirming whether or not the simulation result acquired when the clock frequency of each block is lowered is within the allowable range.

[0087]

[0088] Figure 7 is a block diagram for showing an example of the functional configuration of the improved program 116B according to the second embodiment. refer to Figure 7 , as a main functional configuration realized by executing the improved program 116B, the information processing apparatus 100 includes a data acquisition unit 31B, a clock frequency determination unit 32B, a conversion ratio setting unit 35B, a priority setting unit 36B, and an error determination unit 38B. In addition, the information processing device 100 also includes an output data holding unit 40B realized by the main storage device 110 and the secondary storage device 120 .

[0089] The output data holding unit 40B holds...

no. 3 example

[0119] In the second embodiment, the configuration in which priority is set based on the processing order of each block has been described. However, in the third embodiment, a configuration in which priority is set based on the fluctuation rate of output data of each block will be described.

[0120]

[0121] Figure 9 is a block diagram for showing an example of the functional configuration of the improved program 116C according to the third embodiment. As a main functional configuration realized by executing the improved program 116C, the information processing apparatus 100 includes a data acquisition unit 31C, a clock frequency determination unit 32C, a conversion ratio setting unit 35C, a priority setting unit 36C, an error determination unit 38C, and a volatility calculation unit 39C. The clock frequency determination unit 32C includes a determination unit 34C and a selection unit 37C. The data acquisition unit 31C, the clock frequency determination unit 32C, the co...

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PUM

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Abstract

The embodiments of the disclosure relate to a program, an information processing device, and an information processing method. A program is executed in an information processing device including a processor and a memory. The program allows the processor to execute a step of, on the basis of a simulation result of a model in the case where a series of blocks having an input block, one or more operation blocks, and an output block are allowed to operate at a predetermined clock frequency, deciding a new clock frequency of a target block that is allowed to operate at a clock frequency lower thanthe predetermined clock frequency, and a step of setting the conversion ratios of conversion blocks so as to execute a simulation of the model in which the target block is allowed to operate at the new clock frequency lower than the predetermined clock frequency and the remaining blocks are allowed to operate at the predetermined clock frequency.

Description

[0001] Cross References to Related Applications [0002] Japanese Patent Application No. 2018-093854 filed on May 15, 2018 (including specification, drawings and abstract) is hereby incorporated by reference in its entirety. technical field [0003] The present disclosure relates to a program, an information processing device, and an information processing method, and relates to a program, an information processing device, and an information processing method used, for example, in simulation of a model in model library development. Background technique [0004] In some cases in system development, the process of the V model is used to develop the system. For example, in the V-model, development proceeds in such a way that in a process prior to the coding process, a developer creates a document, an expert reviews it, and the review results are entered in the next process. [0005] However, due to the increase in the scale and complexity of the system, there are cases where ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F17/50
CPCG06F1/324G06F1/3206G06F30/20Y02D10/00G06F1/08
Inventor 津田哲治福山光树角南利郎
Owner RENESAS ELECTRONICS CORP