A fan-out chip packaging structure and packaging method

A chip packaging structure and chip packaging technology, applied in the direction of semiconductor/solid-state device components, semiconductor devices, electrical components, etc., can solve the problems of low reliability of the packaging structure, stress fracture failure, etc. Reduced shear stress and improved reliability
CN110517992BActive Publication Date: 2021-09-07江苏中科智芯集成科技有限公司
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
江苏中科智芯集成科技有限公司
Publication Date
2021-09-07

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Abstract

The invention discloses a fan-out chip packaging structure and a packaging method. The packaging structure comprises: a plastic package, at least one chip is packaged inside; the device surface of the chip is exposed outside the plastic package; an interconnection layer is arranged on the plastic package. The surface where the surface is located is provided with conductive bumps corresponding to the pads of the chip; the conductive bumps are used to lead the corresponding pads to the upper surface of the interconnection layer; the rewiring layer is arranged on the interconnection layer; The wiring layer is electrically coupled with the bump. Through the interconnection layer arranged between the redistribution layer and the plastic package, the interface stress between the package plastic package and the chip is greatly reduced after passing through the interconnection layer, so that the stress on the redistribution layer can be reduced. It is greatly reduced, even if the thin and narrow heavy wiring is affected by the interface stress, the possibility of fatigue fracture is greatly reduced, and the reliability of the packaging structure is improved.
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Description

technical field

[0001] The invention relates to the technical field of semiconductor integrated circuit packaging, in particular to a fan-out chip packaging structure and packaging method. Background technique

[0002] As the most cost-effective technology in the field of system integration packaging, wafer-level fan-out packaging technology will gradually lead the development direction of future system integration technology by virtue of its advantages of high density, light weight and short size, good heat dissipation performance and good electrical performance. . At present, fan-out packaging technology is developing towards next-generation packaging technologies such as multi-chip, thin packaging and three-dimensional system integration.

[0003] However, there are still many problems to be solved in fan-out packaging technology, among which the reliability of multi-chip integrated rewiring is one of the problems. Specifically, due to the large difference in thermal ex...

Claims

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