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A fan-out chip packaging structure and packaging method

A chip packaging structure and chip packaging technology, applied in the direction of semiconductor/solid-state device components, semiconductor devices, electrical components, etc., can solve the problems of low reliability of the packaging structure, stress fracture failure, etc. Reduced shear stress and improved reliability

Active Publication Date: 2021-09-07
江苏中科智芯集成科技有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] Therefore, the technical problem to be solved by the present invention is to solve the problem that the rewiring in the existing packaging structure is prone to failure due to stress fracture when the expansion coefficients of the chip and the plastic packaging material do not match, and the reliability of the packaging structure is low.

Method used

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  • A fan-out chip packaging structure and packaging method
  • A fan-out chip packaging structure and packaging method
  • A fan-out chip packaging structure and packaging method

Examples

Experimental program
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Effect test

Embodiment 1

[0030] This embodiment provides a fan-out chip packaging structure, such as figure 1 As shown, the packaging structure includes: a plastic package body 1 , an interconnection layer 2 and a redistribution layer 3 .

[0031] Such as figure 1 As shown, at least one chip 11 is packaged inside the plastic package 1 , and the device surface of the chip 11 is exposed outside the plastic package 1 . Here, the device surface of the chip 11 refers to the surface where the pads of the chip 11 are located. Specifically, the chip 11 can be first mounted on the substrate 4 according to the direction that the device surface of the chip 11 faces the substrate 4, and then mounted on the substrate 4. The molding compound is injected to form the molding layer 12 that encapsulates five surfaces of the chip 11 except the device surface, and then the molding layer 12 and the chip 11 are peeled off from the substrate 4 to form the molding body 1 .

[0032] Such as figure 1 As shown, the interconn...

Embodiment 2

[0040] This embodiment provides a fan-out chip packaging method, and the packaging structure in Embodiment 1 can be prepared according to the method and its preferred implementation, and what has been explained will not be repeated.

[0041] The fan-out chip packaging method provided in this embodiment, such as figure 2 shown, including the following steps:

[0042] S201: Provide a plastic package.

[0043] here, as image 3 As shown, at least one chip 11 is packaged inside the plastic package 1 , and the device surface of the chip 11 is exposed outside the plastic package 1 .

[0044] Specifically, such as image 3 As shown, the plastic package 1 can be prepared by the following steps:

[0045] Step A1: pasting a first temporary bonding glue 41 on a substrate 4 .

[0046] Step A2: paste the chip 11 on the first temporary bonding glue 41 according to the direction that the device surface of the chip 11 faces the first temporary bonding glue 41 .

[0047] Step A3: dispos...

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Abstract

The invention discloses a fan-out chip packaging structure and a packaging method. The packaging structure comprises: a plastic package, at least one chip is packaged inside; the device surface of the chip is exposed outside the plastic package; an interconnection layer is arranged on the plastic package. The surface where the surface is located is provided with conductive bumps corresponding to the pads of the chip; the conductive bumps are used to lead the corresponding pads to the upper surface of the interconnection layer; the rewiring layer is arranged on the interconnection layer; The wiring layer is electrically coupled with the bump. Through the interconnection layer arranged between the redistribution layer and the plastic package, the interface stress between the package plastic package and the chip is greatly reduced after passing through the interconnection layer, so that the stress on the redistribution layer can be reduced. It is greatly reduced, even if the thin and narrow heavy wiring is affected by the interface stress, the possibility of fatigue fracture is greatly reduced, and the reliability of the packaging structure is improved.

Description

technical field [0001] The invention relates to the technical field of semiconductor integrated circuit packaging, in particular to a fan-out chip packaging structure and packaging method. Background technique [0002] As the most cost-effective technology in the field of system integration packaging, wafer-level fan-out packaging technology will gradually lead the development direction of future system integration technology by virtue of its advantages of high density, light weight and short size, good heat dissipation performance and good electrical performance. . At present, fan-out packaging technology is developing towards next-generation packaging technologies such as multi-chip, thin packaging and three-dimensional system integration. [0003] However, there are still many problems to be solved in fan-out packaging technology, among which the reliability of multi-chip integrated rewiring is one of the problems. Specifically, due to the large difference in thermal ex...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L23/31H01L23/485H01L23/488H01L21/56H01L21/60
CPCH01L23/3107H01L23/485H01L24/02H01L24/03H01L21/568H01L2224/0231H01L2224/0233H01L2224/02373H01L2224/02379H01L2224/18H01L2224/24137H01L2224/96H01L2924/3511
Inventor 姚大平
Owner 江苏中科智芯集成科技有限公司
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