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Semiconductor structure, forming method thereof and SRAM (Static Random Access Memory)

A technology of semiconductor and gate structure, which is applied in the direction of semiconductor devices, transistors, and electrical solid-state devices, etc., can solve the problems of SRAM electrical performance to be improved, reduce the probability of bridging, and optimize electrical performance.

Active Publication Date: 2019-12-17
SEMICON MFG INT (SHANGHAI) CORP +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] However, the electrical performance of the SRAM formed by the prior art still needs to be improved

Method used

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  • Semiconductor structure, forming method thereof and SRAM (Static Random Access Memory)
  • Semiconductor structure, forming method thereof and SRAM (Static Random Access Memory)
  • Semiconductor structure, forming method thereof and SRAM (Static Random Access Memory)

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Embodiment Construction

[0018] It can be seen from the background art that the electrical performance of semiconductor devices still needs to be improved. The reason is analyzed in conjunction with a method for forming a semiconductor structure.

[0019] refer to Figure 1 to Figure 3 , showing a structural schematic diagram corresponding to each step of a method for forming a semiconductor structure, Figure 1 to Figure 2 is a top view, image 3 yes figure 2 Sectional view along secant line A1A2.

[0020] refer to figure 1 , providing a base (not marked) for forming an SRAM device, the base includes a substrate 10 and a plurality of discrete fins (not marked) on the substrate 10, the substrate 10 includes a base for forming a first A first PMOS region I of a pull-up transistor, and a second PMOS region II adjacent to the first PMOS region I and used to form a second pull-up transistor, the substrate 10 also includes a The first NMOS region III on the side of the PMOS region I away from the se...

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PUM

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Abstract

The invention discloses a semiconductor structure, a forming method thereof and an SRAM (Static Random Access Memory). The method comprises the steps of forming a base, wherein the base comprises a substrate and a plurality of fin portions positioned on the substrate, the substrate comprises a first PMOS region used for forming a first pull-up transistor and a second PMOS region used for forming asecond pull-up transistor, the fin portion located on the substrate in the first PMOS region is a first fin portion, the fin portion located on the substrate in the second PMOS region is a second finportion, and the fin portion located on the substrate at the junction of the first PMOS region and the second PMOS region is a third fin portion; forming a first gate structure stretching across thefirst fin portion and a second gate structure stretching across the second fin portion; and forming a first doped epitaxial layer in the first fin portion at two sides of the first gate structure, andforming a second doped epitaxial layer in the second fin portion at two sides of the second gate structure. According to the invention, the third fin portion is formed between the first fin portion and the second fin portion, so that the problem of bridging of the first doped epitaxial layer and the second doped epitaxial layer is avoided.

Description

technical field [0001] The invention relates to the field of semiconductors, in particular to a semiconductor structure, a forming method thereof, and an SRAM. Background technique [0002] As a kind of volatile memory, Static Random Access Memory (SRAM) has the advantages of high speed, low power consumption and compatibility with standard processes, and is widely used in PCs, smart cards, digital cameras, multimedia players, etc. field. [0003] A 6T-structured SRAM unit in the prior art usually includes a storage unit and two read-write units. The memory cell includes two pull-up transistors and two pull-down transistors, the two pull-up transistors are connected to the word line, and the two pull-down transistors are connected to the ground line. The memory cell has two storage nodes and two open nodes for storing 1 or 0 signal; the two read-write units are two transfer transistors, one end of each transfer transistor is connected to a storage node and an open node of ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L27/11H10B10/00
CPCH10B10/18H10B10/12
Inventor 金吉松
Owner SEMICON MFG INT (SHANGHAI) CORP