SRAM circuit yield analysis method based on Bayesian model

Abstract

The invention belongs to the technical field of integrated circuits, and relates to a static random access memory circuit yield analysis method in integrated circuit manufacturability design, which comprises the following steps: firstly, reducing dimensions of a disturbance space of a high-dimensional SRAM (Static Random Access Memory) circuit by using mutual information and sequential quadratic programming to realize quick calculation of an optimal translation vector of the high-dimensional SRAM circuit; then establishing a Bayesian model of performance distribution of the low-dimensional andhigh-dimensional SRAM circuits; finally, using priori knowledge of the low-dimensional SRAM circuit, fitting of performance distribution of the high-dimensional SRAM circuit can be greatly accelerated, the simulation frequency of the high-dimensional SRAM circuit is greatly reduced, and the SRAM failure rate meeting the precision requirement is obtained. Experimental results show that the methodprovided by the invention is obviously superior to the best method known internationally at present, and 6-7 times of acceleration ratio can be realized.

Description

technical field [0001] The invention belongs to the technical field of integrated circuits, and relates to a static random access memory circuit (Static Random Access Memory, SRAM) yield analysis method in integrated circuit manufacturability design, in particular to a Bayesian model-based SRAM circuit yield analysis method, This method first uses mutual information (Mutual Information, MI) and sequential quadratic programming (Sequential Quadratic Programming, SQP) methods to quickly calculate the optimal shift vector (OptimalShift Vector, OSV); Finally, using low-dimensional SRAM circuits as prior knowledge can greatly accelerate the fitting of high-dimensional SRAM circuit performance distribution, greatly reduce the number of high-dimensional SRAM circuit simulations, and obtain high-dimensional SRAMs that meet the accuracy requirements failure rate of the circuit. Background technique [0002] The prior art discloses that as the size of the semiconductor manufacturing ...

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Problems solved by technology

Subset Simulation (SUS) [10] is dedicated to analyzing large-scale SRAM circuits, and calculates the failure rate by equivalently decomposing the failure probability of the circuit into a series of conditional probabilities, but SUS relies on Markov Monte Carlo Luo, a large number of sample points are required to achieve relatively high accuracy

Asymptotic Probability Approximation (APA) [11] and Asymptotic Probability Estimation (APE) [12] try to solve the problem of correlation of process parameters in high-dimensional SRAM circuits. APE analyzes the failure rate of high-dimensional SRAM circuits The problem is decomposed into a series of low-dimensional core unit-level failure rate problems under fixed conditions. However, under this decomposition, circuit simulation is still carried out in high-dimensional, requiring a lot of running time

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