Verification platform and verification method for symmetric encryption algorithm based on UVM

Abstract

The invention discloses a verification platform for a symmetric encryption algorithm based on a UVM. The verification platform comprises a top layer, a test case and a verification environment. The verification environment is derived from uvm_env. Required components are integrated and connected to work. The platform comprises a register model, a sequence generator, a sequence, transaction data, adriver, a coverage rate counter, an input monitor, an output monitor, a scoreboard, a reference model, an input interface and an output interface. Transaction data is generated through the sequence,and random excitation is transmitted to the reference model and the DUT module through driving. Then, the operation results of the reference model and the DUT module are transmitted to the scoreboard,the scoreboard performs data comparison to judge the functional verification condition, and meanwhile, coverage rate check is performed through the coverage rate model to ensure that functional verification simulation is normal. According to the invention, the symmetric encryption algorithm is not limited, the function verification of various encryption symmetric algorithms can be realized, and the verification platform has good reusability and reusability.

Description

technical field [0001] The invention relates to the field of cryptographic algorithm verification, and more specifically, to a verification platform and verification method of a UVM-based symmetric encryption algorithm. Background technique [0002] At present, the integrated circuit industry is growing rapidly in my country. With the continuous development of integrated circuit manufacturing technology and the rapid improvement of chip integration, the gate-level scale of chips has developed from tens of thousands of gates many years ago to millions of gates at present. The functional complexity that can be realized even surpasses the development speed of integration predicted by Moore's Law. Due to the rapid increase in the complexity of chip functions, the verification work occupies most of the entire development cycle, which seriously affects the time to market of the chip. [0003] The traditional verification method is to use the Verilog language to build a simple veri...

AI Technical Summary

Problems solved by technology

At the same time, this method is suitable for directional testing, and it is difficult to conduct non-directional testing through various test vectors, so the efficiency of verifying symmetric encryption algorithms is low and cannot be reused

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