Readout circuit and readout method of multi-level phase change memory
A phase change memory and readout circuit technology, applied in the field of microelectronics, can solve the problems of inability to read out multi-bit data of multi-level phase change memory, inability to distinguish resistance states, etc., and achieve the effect of good scalability and speed improvement
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Embodiment 1
[0062] combine figure 1 and figure 2 As shown, a readout circuit of a multi-level phase-change memory proposed by the present invention is applied to a memory array 20 provided with a phase-change memory unit 21, and the phase-change memory unit 21 stores N-bit binary data;
[0063] The readout circuit is used to divide N stages and read the N-bit binary data of the target phase-change memory unit 21 bit by bit in the order from high to low. The readout circuit includes a read current generation circuit 1, a reference current source circuit 50, a reference Source selection circuit 40, comparison circuit 3 and buffer inverter circuit 7;
[0064] The read current generation circuit 1 is connected to the comparison circuit 3 and the memory array 20, and the read current generation circuit 1 is used to transmit the read current Iread corresponding to the current state of the target phase-change memory unit 21 to the comparison circuit 3;
[0065] The reference current source ci...
Embodiment 2
[0105] The readout circuit of embodiment 2 is applied to the phase-change memory unit 21 that stores two-bit binary data, and the phase-change memory unit 21 stores 2bit-4state, combined with image 3 As shown, the resistance area of the phase change unit is divided into four parts to represent four states "11", "10", "01" and "00". The four states are divided by R1, R2 and R3, and the three reference current sources Iref1 , Iref2 and Iref3 are determined by the resistance value at the demarcation point.
[0106] to combine Figure 3 to Figure 7 As shown, the phase change memory cell 21 has four storage states in total, from low resistance to high resistance are 11, 10, 01 and 00 respectively. The resistance value is less than R2 is 11 and 10, the resistance value is greater than R2 is 01 and 00; in 11 and 10, the resistance value is less than R1 is 11, the resistance value is greater than R1 is 10; in 01 and 00, the resistance value The resistance value smaller than R3 is...
Embodiment 3
[0144] to combine Figure 8As shown, Embodiment 3 provides a readout method of a multi-level phase-change memory, which is applied to a memory array 20 provided with a phase-change memory unit 21, and the phase-change memory unit 21 stores N-bit binary data, according to Read the N-bit binary data of the target phase-change memory cell 21 bit by bit in order to the lower bit, the readout method includes N stages, and the M stage includes steps:
[0145] Step S101: Obtain the read current Iread corresponding to the current state of the target phase-change memory unit 21;
[0146] Step S102: Obtain a reference current, wherein, when M=1, select the initial reference current, and when M>1, select the reference current of the corresponding stage according to the previously read data bits;
[0147] Step S103: Comparing the read current Iread with the reference current in the corresponding stage to obtain a read voltage signal;
[0148] Step S104: processing the readout voltage si...
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