A hardware retransmission circuit and method for aggregated retransmission of data subframes

A data frame and circuit technology, applied in digital transmission systems, electrical components, transmission systems, etc., can solve the problems of throughput impact, increase the load of the main processor, and low efficiency, so as to speed up processing speed, improve transmission throughput, The effect of reducing the load

Active Publication Date: 2022-01-21
浙江科睿微电子技术有限公司
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  • Application Information

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Problems solved by technology

[0004] The embodiment of the present application provides a hardware retransmission circuit and method for aggregation and retransmission of data subframes, which solves the problem that the analysis of BA frames in the prior art and the aggregation and retransmission of subframes are processed by the control layer, and the efficiency is low. The overall throughput of the system has a greater impact and increases the load on the main processor

Method used

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  • A hardware retransmission circuit and method for aggregated retransmission of data subframes
  • A hardware retransmission circuit and method for aggregated retransmission of data subframes
  • A hardware retransmission circuit and method for aggregated retransmission of data subframes

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Embodiment 1

[0027] Such as figure 1 As shown, this embodiment provides a hardware retransmission circuit for aggregated retransmission of data subframes, including:

[0028] A register 13, wherein N descriptors corresponding to N initial transmission subframes are stored in the register 13, where N is a positive integer greater than 1, and the register 13 only stores descriptors, which is more economical than directly storing the initial transmission subframes Register 13 scale. The N descriptors corresponding to the N initial transmission subframes stored in the register 13 may be given by the control layer.

[0029] Single block confirmation BA frame analysis circuit 11, configured to analyze the received current BA frame to obtain the first information associated with the retransmission subframe, the current BA frame is used to represent each subframe in the aggregation frame sent last time The frame transmission situation, the initial transmission subframe includes the retransmissio...

Embodiment 2

[0078] Based on the same inventive concept, such as figure 2 As shown, this embodiment provides a hardware retransmission method for aggregated retransmission of data subframes, which is applied to any hardware retransmission circuit described in Embodiment 1, including:

[0079] Step S101: Analyze the received BA frame to obtain the first information associated with the retransmission subframe, the current BA frame is used to represent the transmission status of each subframe in the aggregation frame sent last time, the initial transmission The subframe includes the retransmission subframe;

[0080] Step S102: update the descriptor corresponding to the retransmission subframe stored in the register according to the first information;

[0081] Step S103: According to the updated descriptor corresponding to the retransmission subframe, read the retransmission subframe from the main storage area and send it.

[0082] As an optional embodiment, the hardware retransmission meth...

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Abstract

The invention discloses a hardware retransmission circuit for aggregated retransmission of data subframes, comprising: a register storing N descriptors corresponding to N initial transmission subframes, where N is a positive integer greater than 1; The block confirmation BA frame analysis circuit is used to analyze the received current BA frame to obtain the first information associated with the retransmission subframe; the retransmission aggregation circuit is used to store the information stored in the The descriptor corresponding to the retransmission subframe in the register is updated; the system memory reading module is used to read the retransmission from the main storage area according to the updated descriptor corresponding to the retransmission subframe subframe and send. The present invention solves the defects of the prior art that the analysis of BA frames and the aggregation and retransmission of subframes are processed by the control layer, which has low efficiency, has a great impact on the overall throughput of the system and increases the load of the main processor.

Description

technical field [0001] The present invention relates to the technical field of wireless communication, in particular to a hardware retransmission circuit and method for aggregation and retransmission of data subframes. Background technique [0002] In order to ensure that the control layer supports high throughput and reduce the control layer overhead caused by the separate transmission of data packets, in the 802.11n standard, Aggregation Media Protocol Data Unit (A-MPDU) and single Block acknowledgment (Block Acknoledgement, BA) frame technology. The so-called aggregated media layer protocol data unit (A-MPDU) and single block acknowledgment (BA) frame technology means that the control layer aggregates multiple media layer protocol data units (Media Protocol Data Unit, MPDU) with the same receiver address into one The aggregated frame is sent to the PHY, and the PHY sends the aggregated frame to the receiving end, and the receiving end will return a BA frame carrying the ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H04L1/16
CPCH04L1/1607
Inventor 不公告发明人
Owner 浙江科睿微电子技术有限公司
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