Neural network accelerator

A neural network and accelerator technology, applied in biological neural network models, neural architecture, physical implementation, etc., can solve the problems of low neural network operation efficiency and inability to make full use of convolutional neural networks, so as to avoid memory cache operations and save operations The effect of time and speed

Active Publication Date: 2020-01-31
陈小柏
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] In order to solve the problem that the existing technology cannot make full use of the characteristics of the convolutional neural network, resulting in low computational efficiency of the neural network, a neural network accelerator is provided, which can improve the computational efficiency of the neural network and save computational time

Method used

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Embodiment 1

[0064] Such as figure 1 Shown, a kind of neural network accelerator, described neural network accelerator is used for connecting global control module Glb, the first direct memory access module DMA, memory DDR3; Described neural network accelerator includes the second direct memory access module DMA, convolution Module conv, single data processing module sdp, plane data processing module pdp, channel data processing module cdp, probability calculation module softmax;

[0065] The convolution module conv performs multiplication and addition operations on input data;

[0066] The single data processing module sdp is used to sequentially perform normalization, activation function, and proportional operation processing on the data;

[0067] The plane data processing module pdp is used to perform maximum pooling, minimum pooling, and average pooling processing on data;

[0068] The channel data processing module cdp is used to perform channel splicing, plane rearrangement, and ma...

Embodiment 2

[0105] The convolution module described in this embodiment, its specific operation method includes the following steps:

[0106] S1: Set the weight weight of a single convolution kernel to size×size; among them, size=1, 2, 3...n, and the number of PE operation units in the strip array is Mk; in this embodiment, Mk=5;

[0107] S2: Since the feature feature is too large to be loaded into the ping-pong RAM at one time, it is necessary to segment the feature feature. The schematic diagram of the segmentation is as follows Figure 16 As shown, this embodiment needs to split in two directions. The first is the height H direction segmentation, which is divided into m parts, and m is a positive integer; for example, this embodiment is divided into 4 points, then H0+H1+H2+H3=H; In this embodiment, the feature feature is divided into m*m parts. For example, this embodiment is divided into 4 parts, then C0+C1+C2+C3=C, the entire feature feature is divided into 4×4=16 sub-features;

[...

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Abstract

The invention discloses a neural network accelerator. The neural network accelerator is used for being externally connected with a global control module, a first direct memory access module DMA and amemory. The neural network accelerator comprises a second direct memory access module DMA, a convolution module, a single data processing module, a plane data processing module, a channel data processing module and a probability calculation module which are connected in sequence in an assembly line mode; the convolution module performs multiply-add operation on the data; the single data processingmodule performs normalization, proportional operation and activation function processing; the plane data processing module performs maximum pooling, minimum pooling and average pooling processing; the channel data processing module performs channel splicing, surface rearrangement and matrix replacement processing; the probability calculation module finds out five maximum values in the data and completes probability operation of the five maximum values; the second DMA transmits the data to a convolution module; and the convolution module and the channel data processing module share one DMA control bus.

Description

technical field [0001] The present invention relates to the technical field of integrated circuits, and more specifically, to a neural network accelerator. Background technique [0002] Convolutional Neural Network (CNN) is an important algorithm for deep learning, and it has a very wide range of applications in the field of computer vision, especially image recognition. At present, almost all identification and detection problems use convolutional neural network as the preferred method, and various IT giants in the world are also competing to carry out related research. [0003] From the perspective of the computer, the image is actually a two-dimensional matrix. The work of the convolutional neural network is to extract features from the two-dimensional array by using operations such as convolution and pooling, and to recognize the image. Theoretically, as long as the data can be converted into a two-dimensional matrix, it can be identified and detected by using a convolu...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06N3/04G06N3/063
CPCG06N3/063G06N3/045Y02D10/00
Inventor 陈小柏赖青松
Owner 陈小柏
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