Deep neural network accelerator based on hybrid precision storage

Abstract

The invention discloses a deep neural network accelerator based on hybrid precision storage, and belongs to the technical field of calculation, reckoning and counting. The accelerator comprises an on-chip cache module, a control module, a bit-width-controllable multiply-add-batch calculation module, a nonlinear calculation module, a register array and a Huffman decoding module based on double lookup tables, effective bit and sign bit parameters of the weight are stored in the same memory, so that mixed-precision data storage and analysis are realized, and multiply-add operation of mixed-precision data and weight is realized. Through data storage analysis based on mixed precision and Huffman decoding based on a dual lookup table, compression and storage of data and weights under different precision are realized, data streams are reduced, and low-power-consumption data scheduling based on a deep neural network is realized.

Description

technical field [0001] The invention discloses a deep neural network accelerator based on mixed-precision storage, relates to the design of a digital-analog hybrid integrated circuit of an artificial intelligence neural network, and belongs to the technical field of calculation, calculation and counting. Background technique [0002] Deep neural network has been widely researched and applied due to its superior performance. The current mainstream deep neural network has hundreds of millions of connections, and its memory-intensive and computing-intensive characteristics make it difficult for them to be mapped to embedded systems with extremely limited resources and power consumption. In addition, the current trend of deep neural networks towards more accurate and powerful functions makes the scale of deep neural networks, the required storage space become larger and larger, and the computational overhead and complexity become larger and larger. [0003] The traditional cust...

AI Technical Summary

Problems solved by technology

Therefore, the design difficulties of deep neural network accelerators are attributed to two points: 1) The scale of deep neural networks is getting larger and larger, and the memory access problem has become the biggest bottleneck in neural network operations, especially when the size of the weight matrix is ​​larger than the cache capacity. , the advantages of the neural network cannot be fully utilized; 2) The structure of the deep neural network determines that its basic operations are a large number of multiplication and accumulation operations, and multiplication has always been an arithmetic operation that consumes a lot of hardware resources, has a long delay and consumes a lot of power. The speed and power consumption of operations determine the performance of deep neural network accelerators

[0004] Traditional deep neural network accelerators mainly improve the reliability and stability of the system by instantiating a large number of multiply-add computing units and storage units. A large amount of chip area and a large amount of operating power limit the use of neural network accelerators in portable interactive devices. Deployment in

In order to solve these problems, the most popular technology at present is to perform binary processing on weight data. This processing method can greatly simplify network computing data scheduling and memory access mode, but its network accuracy loss is large, and the system stability needs to be verified.

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