Combined tree model-based virtual metrology (VM) method of resistivity of semiconductor PVD manufacturing process

Abstract

The invention discloses a combined tree model-based virtual metrology (VM) method of resistivity of a semiconductor PVD manufacturing process. The method includes the following steps: 1, constructingan integrated tree combination model on the basis of a combination prediction method [7], and carrying out online virtual metrology on electrical parameters of WAT (Wafer Acceptance Test); and 2, by the integrated tree combination model, using 4 types of integrated trees as base learners to carry out preliminary virtual metrology on wafer manufacturing process status information, transforming prediction results of the four base learners into meta feature vectors to use the same as input of an integrated tree meta learner, and carrying out further virtual metrology. Compared with common virtualmetrology models of LASSO, PLSR, SVR, GPR and ANN models, the integrated tree model is more suitable for use in virtual metrology on PVD manufacturing processes, the integrated tree combination modelhas higher prediction accuracy than a single integrated tree virtual-metrology model, real-time monitoring and early warning can be achieved, and early warning time is greatly advanced.

Description

technical field [0001] The invention relates to the technical field of resistivity virtual measurement, in particular to a method for resistivity virtual measurement of a semiconductor PVD process based on a combination tree model. Background technique [0002] In semiconductor manufacturing enterprises, the wafer process mainly includes photolithography (Photo), etching (Etch), diffusion (Diffusion, Diff), chemical-mechanical polishing (Chemical-Mechanical Polish, CMP) and other processes. The control of the process is the process of wafer production. very important link. At this stage, Wafer Acceptance Test (WAT) is the primary quality assurance of wafer output. It is a non-productive electrical testing technology used to monitor wafer process status, including device characteristics and resistance. devices, capacitors, connectivity, continuity, spacing, insulation, leakage. In the existing semiconductor manufacturing process, the wafer acceptability test is to detect th...

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Problems solved by technology

[0004] Most of the above-mentioned virtual measurement methods use a single model or method for prediction, and the model achieves a certain prediction accuracy, but there is a problem that the information angle of model learning is single, and the prediction accuracy has room for further improvement

The reason is that under the conditions of complex semiconductor wafer manufacturing processes, there are many uncertain factors such as randomness or fuzziness. If the model can capture more uncertain factors, the prediction accuracy of the model will be further improved. Therefore, this field The technicians provide a virtual resistivity measurement method of semiconductor PVD process based on the combined tree model to solve the problems raised in the above-mentioned background technology

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