Semiconductor structure forming method

Abstract

The invention provides a semiconductor structure forming method. The method comprises the steps that an etching target layer is formed on a semiconductor substrate; a patterned mask layer is formed onthe etching target layer; the patterned mask layer is used as a mask; the etching target layer is etched, so that a plurality of wirings arranged at intervals are formed on the etching target layer;the mask layer includes a plurality of bumps, and the width of the bumps is corresponding to the line width of the corresponding wirings; and the height of the bumps is set based on the material and height of the etching target layer. According to the invention, a grayscale lithography method, a nano-imprint method, a grayscale reticle lithography method, and an ion beam gas-assisted deposition method are used to form the patterned mask layer; dry etching is used to transfer the pattern of the mask layer into the etching target layer of the semiconductor structure; process steps in the processof forming the semiconductor structure can be reduced; the process complexity can be reduced; and an ideal fine pattern can be acquired at the same time.

Description

technical field [0001] The invention relates to the technical field of semiconductor devices, in particular to a method for forming a semiconductor structure. Background technique [0002] At present, for fine patterns formed by alternately arranged lines (lines) and spaces (spaces) on a substrate, a self-aligned double patterning (Self-Aligned Double Patterning, SADP) technique is generally used to form. [0003] The existing method for forming a fine pattern using SADP technology includes the following steps: depositing an etching target layer on a semiconductor substrate, coating a photoresist layer on the surface of the etching target layer, and exposing and developing to pattern the photoresist layer. The width of the photoresist layer is obtained to define the line width and space width of the fine pattern; the oxide layer is deposited on the surface of the patterned photoresist layer and the surface of the exposed etching target layer; the oxide layer is anisotropical...

AI Technical Summary

Problems solved by technology

Furthermore, the oxide layer is deposited on the surface of the patterned photoresist layer and the surface of the exposed etching target layer. For smaller-sized fine patterns, it is difficult to obtain an ideal sidewall layer

Moreover, the existing SADP technology needs to form a sidewall layer with the help of a patterned photoresist layer, the steps are relatively complicated, and the production efficiency is low when it is realized.

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