Controllable tracking debugging method and system for RISC-V processor

A RISC-V, trace debugging technology, applied in electrical digital data processing, software testing/debugging, instruments, etc., can solve the problems of inflexible acquisition of RISC-V processors, reduce debugging cycle, reduce debugging difficulty, etc. The effect of reducing the need for long-term tracking and debugging, reducing the debugging cycle, and reducing the difficulty of debugging
CN110795350AActive Publication Date: 2020-02-14SHANDONG INSPUR SCI RES INST CO LTD
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
SHANDONG INSPUR SCI RES INST CO LTD
Publication Date
2020-02-14

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Abstract

The invention discloses a controllable tracking debugging method and system for an RISC-V processor, and belongs to the processor debugging field, solving the technical problem about how to realize quick positioning and debugging. According to the technical scheme, the controllable tracking debugging method comprises the following steps that S1, an upper computer generates a tracking debugging instruction, an enable signal obtained by general register data and a general register address needing to be obtained, packages the debugging tracking instruction and sends the debugging tracking instruction to a PL end through a gigabit Ethernet interface; S2, the PL end receives a debugging tracking instruction sent by an upper computer through a gigabit Ethernet module, and forwards the whole debugging tracking instruction to a tracking instruction acquisition module; S3, a tracking instruction acquisition module analyzes the debugging tracking instruction; S4, whether an enable signal is acquired or not is judged; and S5, the instruction and the general register data are acquired and sent to the upper computer for analysis. The controllable tracking debugging system comprises an upper computer, a gigabit Ethernet module, a tracking instruction acquisition module, an FIFO module and an RISC-V processor IP core.
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Description

technical field

[0001] The invention relates to the field of processor debugging, in particular to a controllable tracking and debugging method and system for a RISC-V processor. Background technique

[0002] RISC-V (Fifth Generation Reduced Instruction Set Computer) is an open instruction set architecture based on the principle of reduced instruction set computing. It has the characteristics of complete open source, simple structure, easy portability, and modular design. Based on its open source characteristics, the non-profit organization RISC-V Foundation was established. As of January 2019, more than 200 members have joined the non-profit organization RISC-V Foundation. The China RISC-V Industry Alliance also has more than fifty RISC-V-related companies and more than ten universities and research institutions joining.

[0003] When designing RISC-V processor IP, the debug unit is often an important part of it. Processor IP debugging methods are mainly interactive debug...

Claims

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