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Controllable tracking debugging method and system for RISC-V processor

A RISC-V, trace debugging technology, applied in electrical digital data processing, software testing/debugging, instruments, etc., can solve the problems of inflexible acquisition of RISC-V processors, reduce debugging cycle, reduce debugging difficulty, etc. The effect of reducing the need for long-term tracking and debugging, reducing the debugging cycle, and reducing the difficulty of debugging

Active Publication Date: 2020-02-14
SHANDONG INSPUR SCI RES INST CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, this technical solution cannot flexibly obtain RISC-V processor operating instructions and register data within a specific period of time, and can quickly locate problems encountered in debugging, reducing the debugging cycle and reducing the difficulty of debugging

Method used

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  • Controllable tracking debugging method and system for RISC-V processor
  • Controllable tracking debugging method and system for RISC-V processor

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Embodiment 1

[0043] as attached figure 1 As shown, the controllable tracking debugging method of the RISC-V processor of the present invention, the method steps are as follows:

[0044] S1. The upper computer generates the enable signal for tracking and debugging instructions and general register data acquisition and the address of the general register to be obtained, packs and debugs the tracking instructions, and sends them to the PL terminal through the Gigabit Ethernet interface; wherein, the debugging and tracking instructions include acquiring instructions. Enable and disable signals and register codes for obtaining general-purpose register data. By enabling and disabling signals for debugging and tracking instructions, the time point for obtaining instructions can be effectively controlled, reducing the amount of instruction analysis data in the later stage; the production and sending time of debugging and tracking instructions can be shortened. Control, which can be set by the debu...

Embodiment 2

[0058] as attached figure 2 Shown, the controllable tracking debugging system of RISC-V processor of the present invention, this system comprises upper computer, Gigabit Ethernet module, tracking instruction acquisition module, FIFO module and RISC-V processor IP core, upper computer and gigabit The Gigabit Ethernet module communicates with each other, the Gigabit Ethernet module communicates with the tracking instruction acquisition module, the tracking instruction acquisition module communicates with the RISC-V processor IP core, and the tracking instruction acquisition module stores data to the FIFO module, and the FIFO module sends data to Gigabit Ethernet module;

[0059] Among them, the upper computer is used to generate the enable signal for tracking and debugging instructions and general register data acquisition, as well as the address of the general register to be obtained, package the debugging and tracking instructions, and send them to the PL terminal through the...

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Abstract

The invention discloses a controllable tracking debugging method and system for an RISC-V processor, and belongs to the processor debugging field, solving the technical problem about how to realize quick positioning and debugging. According to the technical scheme, the controllable tracking debugging method comprises the following steps that S1, an upper computer generates a tracking debugging instruction, an enable signal obtained by general register data and a general register address needing to be obtained, packages the debugging tracking instruction and sends the debugging tracking instruction to a PL end through a gigabit Ethernet interface; S2, the PL end receives a debugging tracking instruction sent by an upper computer through a gigabit Ethernet module, and forwards the whole debugging tracking instruction to a tracking instruction acquisition module; S3, a tracking instruction acquisition module analyzes the debugging tracking instruction; S4, whether an enable signal is acquired or not is judged; and S5, the instruction and the general register data are acquired and sent to the upper computer for analysis. The controllable tracking debugging system comprises an upper computer, a gigabit Ethernet module, a tracking instruction acquisition module, an FIFO module and an RISC-V processor IP core.

Description

technical field [0001] The invention relates to the field of processor debugging, in particular to a controllable tracking and debugging method and system for a RISC-V processor. Background technique [0002] RISC-V (Fifth Generation Reduced Instruction Set Computer) is an open instruction set architecture based on the principle of reduced instruction set computing. It has the characteristics of complete open source, simple structure, easy portability, and modular design. Based on its open source characteristics, the non-profit organization RISC-V Foundation was established. As of January 2019, more than 200 members have joined the non-profit organization RISC-V Foundation. The China RISC-V Industry Alliance also has more than fifty RISC-V-related companies and more than ten universities and research institutions joining. [0003] When designing RISC-V processor IP, the debug unit is often an important part of it. Processor IP debugging methods are mainly interactive debug...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F11/36G06F5/06
CPCG06F11/3636G06F11/3644G06F5/065Y02D10/00
Inventor 王帅王子彤赵鑫鑫
Owner SHANDONG INSPUR SCI RES INST CO LTD
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