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Debugging system for RISC-V processor and debugging signal transmission method

A RISC-V, signal transmission technology, applied in the field of signal transmission, can solve the problems of use and inability, achieve the effect of low design complexity, small number of pins, and meet debugging requirements

Pending Publication Date: 2020-02-28
NANJING QINHENG MICROELECTRONICS CO LTD
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  • Abstract
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  • Application Information

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  • Debugging system for RISC-V processor and debugging signal transmission method
  • Debugging system for RISC-V processor and debugging signal transmission method
  • Debugging system for RISC-V processor and debugging signal transmission method

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Embodiment Construction

[0040] The present invention will be further explained below in conjunction with the drawings and specific embodiments.

[0041] Such as figure 2 As shown, a debugging system for a RISC-V processor includes a debugging host 101, an interface converter 102, a debugging module interface 104, a debugging module 107, and a RISC-V processor core 108, a debugging module interface 104, and a debugging module 107 And the RISC-V processor core 108 together form the RISC-V platform 109. The debugging host 101 and the interface converter 102 have a two-way communication connection. The interface converter 102 and the debugging module interface 104 are connected by two signal lines 103, a clock signal line and a data signal line. The data signal line is a bidirectional signal line. The debugging module interface 104 has two pins, two Each pin is connected to two signal wires 103, and the debugging module interface 104 can be integrated on the debugging module 107.

[0042] The debugging hos...

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Abstract

The invention discloses a debugging system for an RISC-V processor and a debugging signal transmission method. The system comprises a debugging host, an interface converter, a debugging module interface and a debugging module. The interface converter converts request data which are sent by the debugging host and accord with a JTAG protocol into a two-line protocol and then transmits the two-line protocol to the debugging module. The feedback data which are responded by the debugging module and accord with the two-line protocol are converted into a JTAG protocol and then sent to the debugging host. The debugging module is small in number of pins, and can be compatible with mainstream RISC-V debugging host software, is low in design complexity, and meets the debugging demands of scenes withstrict requirements for the packaging size of a chip.

Description

Technical field [0001] The invention belongs to the field of signal transmission, and particularly relates to a debugging signal transmission method for a RISC-V processor. Background technique [0002] In the RISC-V Debug Specification issued by the RISC-V Foundation, the debugging system is mainly composed of a debug module (Debug Module, DM), a debug module interface (Debug Module interface, DMI), and a debug transport module (Debug Transport). Module, DTM), Debug Transport Hardware (DTH) and Debug Host (Debug Host). Among them, DTM is mainly responsible for receiving the data sent by the debugging host to the debugging module through DTH, or sending the data reported by the debugging module DM to the debugging host. Therefore, DTM is the only way for the communication between the debugging host and the debugging device. [0003] The RISC-V debugging architecture document uses the IEEE 1149.1 standard, namely JTAG, as the debugging transmission module to realize the communicati...

Claims

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Application Information

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IPC IPC(8): G06F13/38G06F13/42G06F11/36
CPCG06F13/387G06F13/4221G06F11/3656
Inventor 韩春阙庆河
Owner NANJING QINHENG MICROELECTRONICS CO LTD
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