Signal processing method and device and selection circuit
A technology for selecting circuits and signal processing, which is applied in the field of communication and can solve problems such as long delay time
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Embodiment 1
[0033] figure 1 A flowchart of a signal processing method provided by an embodiment of the present invention; figure 2 A schematic diagram of an R-to-N selection circuit provided by an embodiment of the present invention. The embodiment of the present invention aims at the selection method of the existing unallocated items by judging whether each item in the bit vector is unallocated one by one to select unallocated items in the bit vector, and the problem of long delay time provides signal processing method. Such as figure 1 As shown, the specific steps of the method are as follows:
[0034] Step S101. Obtain a bit vector corresponding to the queue to be processed, and convert the bit vector to obtain L groups of signals corresponding to the bit vector, each group of signals corresponding to each item in the bit vector.
[0035] In this embodiment, a bit vector is used to indicate the usage of queues to be processed, each item in the bit vector is used to indicate the al...
Embodiment 2
[0062] image 3 A schematic structural diagram of a processing unit provided by an embodiment of the present invention; Figure 4 A schematic structural diagram of another processing unit provided by an embodiment of the present invention; Figure 5 A schematic structural diagram of a basic selection logic circuit of 4 out of 8 provided by the embodiment of the present invention.
[0063] On the basis of the first embodiment above, in this embodiment, the basic selection logic circuit for selecting M from N includes N sub-selection logic modules. Wherein, each sub-selection logic module includes N processing units.
[0064] Each processing unit is used for:
[0065] Receive two groups of signals, and according to the value of a group of signals received by the receiving terminal as the enabling terminal, determine one group from the two groups of signals as the unassigned group signal to be determined, and determine the other group as the assigned group signal to be determi...
Embodiment 3
[0084] Image 6 A schematic structural diagram of a 32-to-4 selection circuit provided by an embodiment of the present invention. On the basis of the second embodiment above, the embodiment of the present invention provides a selection circuit for selecting R from N. Specifically, in a recursive manner, the R-select-N selection circuit is composed of a plurality of M-select N basic selection logic circuits.
[0085] The selection circuit for selecting R from N includes: a first-stage selection logic module for receiving R group signals, and a second-stage selection logic module connected to the first-stage selection logic module.
[0086] The first-stage selection logic module includes a selection circuit for K to select N and a selection circuit for T to select N, and the selection circuit for K to select N and the selection circuit for T to select N include at least one M to select N Basic selection logic circuit where R=K+T.
[0087] The second-stage selection logic modu...
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