Neural network acceleration system based on FPGA

A neural network and acceleration system technology, applied in the fields of artificial intelligence and electronics, can solve the problems of computing acceleration, increasing costs, consuming large resources and energy, etc., and achieve the effects of increasing inference speed, reducing power consumption, and increasing computing speed

Pending Publication Date: 2020-04-10
FUZHOU UNIVERSITY
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Problems solved by technology

[0003] And with the development of the Internet of Things, deploying the convolutional neural network on the embedded side has to process a large amount of data, which will consume a lot of resources and energy, and embedded device

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  • Neural network acceleration system based on FPGA
  • Neural network acceleration system based on FPGA
  • Neural network acceleration system based on FPGA

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Embodiment Construction

[0017] The technical solution of the present invention will be specifically described below in conjunction with the accompanying drawings.

[0018] The present invention provides an FPGA-based neural network acceleration system. According to the natural parallelism of the convolutional neural network and the sparsity of the fully connected layer, the system reuses computing resources, parallelizes data and pipeline design, and utilizes fully connected The sparsity of the layer design sparse matrix multiplier greatly improves the operation speed and reduces the use of resources, so as to improve the inference speed without affecting the inference accuracy of the convolutional neural network. The system includes a data input module, a convolution processing module, a pooling module, a convolution control module, a non-zero detection module, a sparse matrix multiplier, and a classification output module; the convolution control module controls the data to be convoluted and the neu...

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Abstract

The invention relates to a neural network acceleration system based on FPGA. According to the neural network acceleration system, on the basis of the natural parallelism of a convolutional neural network and the sparsity of a full connection layer, through operation resource reuse, parallel data processing and assembly line design, a sparse matrix multiplier is designed by utilizing the sparsity of the full connection layer, so the operation speed is greatly improved; the use of resources is reduced; and the inference speed is improved under the condition that the inference accuracy of the convolutional neural network is not influenced. According to the invention, through operation resource reuse, parallel data processing and assembly line design, the sparse matrix multiplier is designed by utilizing the sparsity of the full connection layer, so the operation speed is greatly improved; the use of resources is reduced; and under the condition that the inference accuracy of the convolutional neural network is not influenced, the overall power consumption of the system is reduced, and the inference speed is improved.

Description

technical field [0001] The invention belongs to the fields of artificial intelligence and electronics, and in particular relates to an FPGA-based neural network acceleration system. Background technique [0002] With the rapid development and wide application of deep learning in recent years, convolutional neural network (CNN) has become the best method in the field of detection and recognition. It can automatically learn to extract features from data sets, and the more network layers , the extracted features are more global. Through local connection and weight sharing, the generalization ability of the model can be improved, and the accuracy of recognition and classification can be greatly improved. [0003] And with the development of the Internet of Things, deploying the convolutional neural network on the embedded side has to process a large amount of data, which will consume a lot of resources and energy, and embedded devices usually use batteries to maintain work, and...

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Application Information

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IPC IPC(8): G06N3/063
CPCG06N3/063
Inventor 郭太良林志文林志贤张永爱周雄图
Owner FUZHOU UNIVERSITY
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