Debugging verification platform and test method for RISC-V processor system

A RISC-V, processor system technology, applied in fault hardware testing methods, electrical digital data processing, instruments, etc., can solve the problems of cumbersome SoC verification platform construction and high requirements for boards and cards, so as to improve project parallelism and flexible debugging High performance and low hardware resource requirements

Active Publication Date: 2020-04-14
INSPUR SUZHOU INTELLIGENT TECH CO LTD
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  • Claims
  • Application Information

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Problems solved by technology

[0005] Aiming at the problem that the SoC verification platform is cumbersome to build and the requirements for boards are high during the debugging process of the RISC-V system, the present invention provides a debugging verification platform and a testing method for the RISC-V processor system

Method used

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  • Debugging verification platform and test method for RISC-V processor system
  • Debugging verification platform and test method for RISC-V processor system

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Embodiment 1

[0045] like figure 1 As shown, the technical solution of the present invention provides a debugging verification platform of a RISC-V processor system, and the FPGA-based RISC-V processor system starts the SoC verification platform, including a processor soft core, and the processor soft core passes through the bus The module communicates with the RAM storage control module and the UART data control module respectively;

[0046] The platform also includes a mode control module, and the mode control module is connected with the RAM storage control module and the UART data control module respectively;

[0047] The RAM storage control module is connected with a RAM memory; it is used for code instruction storage and program operation;

[0048] The mode control module is connected with a GPIO interface, which is used to generate a control signal to the processor soft core for system mode conversion according to the input signal of the GPIO interface;

[0049]The UART data contro...

Embodiment 2

[0062] like figure 2 As shown, the technical solution of the present invention provides a testing method for a debugging system of a RISC-V processor system. For the debugging platform of Embodiment 1, the RISC-V system startup testing method according to the present invention can be divided into debugging according to GPIO control and update two modes, including the following steps:

[0063] S1: The RISC-V processor starts running;

[0064] S2: The startup code starts to run;

[0065] For the RISC-V processor soft core, it is necessary to correctly configure its operating frequency, BootRom address and RAM bus address. The system startup code includes ZSBL, FSBL, BBL and Kernel. In order to save storage resources, optimize the invalid code as much as possible, optimize and simplify the Kernel, and at the same time, due to the minimal SoC system used, redundant hardware initialization code is saved. The final system startup code file Meet storage and running space requirem...

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Abstract

The invention provides a debugging verification platform and a test method for an RISC-V processor system. The platform comprises a processor soft core which is in communication with an RAM storage control module and a UART data control module through a bus module. The platform further comprises a mode control module, and the mode control module is connected with the RAM storage control module andthe UART data control module. The RAM memory control module is connected with an RAM memory and is used for code instruction storage and program running; the mode control module is connected with a GPIO interface and is used for generating a control signal to the processor soft core according to an input signal of the GPIO interface to perform system mode conversion; the UART data control moduleis connected with a UART interface and is used for controlling to switch the mode of the UART interface according to the change of the system mode.

Description

technical field [0001] The invention relates to the technical field of processor design verification, in particular to a debugging verification platform and a testing method for a RISC-V processor system. Background technique [0002] FPGA is programmable, flexible, stable, fast, and efficient. It is a supplement to ASIC and can also be used as a verification platform for ASIC. [0003] RISC-V is a novel and advanced instruction set, which is widely adopted in processor design due to its forward-looking, compact, extensible and open-source features. [0004] In the design verification process of the processor, the start-up and debugging of the operating system are indispensable processes. The startup file of the system requires storage space such as SD card or Flash, but it is a relatively time-consuming task to build a RISC-V processor SoC verification platform based on FPGA and add related peripherals such as SD card or Flash. The card needs to have an SD card interface,...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F11/22G06F11/267
CPCG06F11/2247G06F11/2273G06F11/267
Inventor 王贤坤
Owner INSPUR SUZHOU INTELLIGENT TECH CO LTD
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