A Convolutional Neural Network Accelerator Architecture with Binarized Weights and Activations

Abstract

The invention relates to a convolutional neural network accelerator architecture in which both weights and activation values ​​are binarized, including: a first memory, a fifth memory and a ninth memory for storing weight data; a memory for storing feature map data The third memory, the fourth memory, the seventh memory and the eighth memory; the second operator, the sixth operator and the tenth operator. The present invention provides a convolutional neural network accelerator architecture in which both weights and activation values ​​are binarized; data multiplication is realized by XOR operation, and XOR can be completed without using multipliers, but using logic resources to complete the operation.

Description

technical field [0001] The invention relates to a convolutional neural network accelerator architecture with binarized weight and activation values, belonging to the technical field of integrated circuit design. Background technique [0002] In recent years, convolutional neural networks have been widely developed in many fields. In the convolutional neural network, due to the large number of parameters of the data, it will take up a relatively high storage space when each parameter is stored in a floating-point number. Therefore, it is often used in the FPGA implementation architecture to use fixed-point numbers to represent each data. representation method. [0003] In the process of forward inference of convolutional neural network, the requirements for data accuracy are low. Some scholars propose to use 16bit, 8bit or even lower bit width to represent data, without having a great impact on the final result. , 1bit data can be used to represent the weight and the value ...

AI Technical Summary

Problems solved by technology

When using FPGA to implement 16-bit wide convolutional neural network, the operation speed is limited by the number of multipliers in FPGA

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