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3d NAND memory device and manufacturing method thereof

A 3DNAND, storage device technology, applied in semiconductor devices, electric solid state devices, electrical components, etc., can solve problems affecting the running speed of 3DNAND storage devices, device stability, etc., achieve small parasitic capacitance, improve running speed and stability. Effect

Active Publication Date: 2022-04-29
YANGTZE MEMORY TECH CO LTD
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0004] However, with the increase of the storage density of 3D NAND storage devices, the size of 3D NAND storage devices is getting smaller and smaller, and the distance between adjacent conductive layers in the device is getting closer and closer, resulting in an increase in the parasitic capacitance between conductive layers. Large, this capacitance not only affects the operating speed of the 3D NAND memory device, but also seriously affects the stability of the device

Method used

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  • 3d NAND memory device and manufacturing method thereof
  • 3d NAND memory device and manufacturing method thereof
  • 3d NAND memory device and manufacturing method thereof

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[0034] The following descriptions of the various embodiments refer to the accompanying drawings to illustrate specific embodiments in which the invention may be practiced. The directional terms mentioned in the present invention, such as [top], [bottom], [front], [back], [left], [right], [inside], [outside], [side], etc., are only for reference The orientation of the attached schema. Therefore, the directional terms used are used to illustrate and understand the present invention, but not to limit the present invention. In the figures, structurally similar elements are denoted by the same reference numerals.

[0035] The present invention aims at the existing 3D NAND storage device, with the increase of storage density, the size of the device is continuously reduced, resulting in the increase of parasitic capacitance, which has a serious impact on the operating speed and stability of the 3D NAND storage device. The embodiment of the present invention uses to solve this probl...

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Abstract

The invention relates to the field of semiconductor devices, and discloses a 3D NAND storage device and a manufacturing method thereof. The above-mentioned 3D NAND storage device includes: a substrate; a stacked layer on the substrate, the stacked layer includes a plurality of laterally extending gate layers and a first insulating layer arranged at staggered intervals; longitudinally extending through the The channel structure of the stacked layer, the channel structure includes a storage function layer, a channel layer and a channel filling layer; a gate spacer extending longitudinally through the stacked layer, between adjacent gate spacers It includes a plurality of channel structures; wherein air gaps are formed in the plurality of first insulating layers. The 3D NAND storage device provided by the present invention reduces parasitic capacitance and improves the operation speed and stability of the storage device by forming an air gap in the first insulating layer in the stacked layers.

Description

technical field [0001] The invention relates to the field of semiconductor devices, in particular to a 3D NAND storage device and a manufacturing method thereof. Background technique [0002] 3D NAND memory devices are non-volatile storage products with low power consumption, light weight and good performance, and are widely used in electronic products, especially digital cameras, MP3 players, mobile phones, global positioning systems (GPS), high-end notebook computers and storage applications for mobile electronic products such as tablets. [0003] In the structure of 3D NAND memory devices, the method of stacking multiple gate layers and insulating layers vertically is adopted, and deep channel holes are formed in the stacked layers (or "stacks"), and memory cells are formed in the deep channel holes. The gate layer in the stacked layer serves as the gate line of each layer of memory cells, thereby realizing a stacked 3D NAND memory device. [0004] However, with the inc...

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L27/11524H01L27/11556H01L27/1157H01L27/11582H10B41/35H10B41/27H10B43/27H10B43/35
CPCH10B41/35H10B41/27H10B43/35H10B43/27
Inventor 刘小欣薛磊薛家倩耿万波黄波
Owner YANGTZE MEMORY TECH CO LTD