Unlock instant, AI-driven research and patent intelligence for your innovation.

Test system and method for FPGA PLL IP core

A test system and test method technology, applied in the field of test systems for FPGAPLLIP cores, can solve problems such as inability to effectively and accurately test phase-locked loops, long test time, etc., and achieve easy analysis of test results, high test efficiency, and simple calculation. Effect

Active Publication Date: 2020-05-08
STATE GRID CORP OF CHINA +3
View PDF11 Cites 4 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] In order to solve the problem that the traditional test method existing in the prior art cannot effectively and accurately test the phase-locked loop, and the test time is long, the present invention provides a test system and method for the FPGA PLL IP core, the test time is short, saving interior space

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Test system and method for FPGA PLL IP core
  • Test system and method for FPGA PLL IP core
  • Test system and method for FPGA PLL IP core

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0064] A specific embodiment for the test system of FPGA PLL IP core is provided below, as figure 2 shown.

[0065] The FPGA chip used in the test is a self-developed FPGA chip. Each FPGA chip contains 8 PLLs with the same design and independent of each other. A PLL is designed with normal mode, zero delay mode and no compensation mode. In normal mode, c0 feedback or c1 feedback can be selected. In zero delay mode, e0 feedback is used. Common mode and zero delay mode are collectively referred to as compensation mode. In the compensation mode, the input frequency range is 15.625MHz~60MHz, and in the non-compensation mode, the input frequency range is 15.625MHz~420MHz. VCO output frequency range is 300MHz~800MHz, c0, c1, e0 output frequency range is 9.375MHz~800MHz, c0, c1, e0 duty cycle range is 0~100%, c0, c1, e0 phase shift range is 0~360 °, the highest signal frequency on the FPGA chip I / O pins does not exceed 200MHz.

[0066] The power supply is E3631A from Agilent, the...

Embodiment 2

[0069] The present invention also provides a kind of test method for FPGA PLL IP core, comprising:

[0070] Step 1: The PC generates a test bit stream code based on a preset test case, and downloads the test bit stream code to the FPGA chip to be tested through the circuit board to be tested;

[0071] Step 2: Simultaneously control the signal source to output a clock signal to the circuit board under test based on the test case;

[0072] Step 3: The FPGA chip to be tested generates an output signal based on the test bit stream code and clock signal obtained by the circuit board to be tested, and transmits it to the PC;

[0073] Step 4: The PC analyzes the output signal and completes the test.

[0074] Specifically, the test is divided into two stages. The first stage is the test preparation stage, including the formulation of test files and the generation of FPGA configuration files. The second phase is the testing phase, including specific testing and testing data analysis....

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The invention provides a test system and a test method for an FPGA PLL IP core. The test system comprises a to-be-tested circuit board, a signal source and a PC, wherein the signal source and the PC are connected with the to-be-tested circuit board; the PC is further connected with the signal source; a to-be-tested FPGA chip is installed on the to-be-tested circuit board; the PC is used for triggering the signal source to generate a clock signal based on a preset test case; the PC is further used for generating a test bit stream code based on the test case and downloading the test bit stream code into the to-be-tested FPGA chip by means of the to-be-tested circuit board; the to-be-tested circuit board is used for transmitting an output signal generated by operation of the to-be-tested FPGAchip based on the test bit stream code and the clock signal to the PC; and the PC is further used for analyzing the output signal of the to-be-tested FPGA chip to complete the test. According to thetest system and the test method, the automatic test of the PLL IP core in the FPGA chip is realized, and the test platform can carry out comprehensive test on the PLL IP core without a built-in self-testing circuit and can further carry out supplementary test on the PLL IP core with the built-in self-test circuit.

Description

technical field [0001] The invention relates to the technical field of integrated circuit measurement, in particular to a test system and method for FPGA PLL IP cores. Background technique [0002] FPGA is a digital integrated circuit that is programmed by users to realize the required logic functions. It not only has the advantages of flexible design, high performance, and fast speed, but also has a short development cycle and low cost, so it has been widely used in the field of digital signal processing. However, with the continuous improvement of the operating frequency of digital systems and the need for greater throughput data processing, digital systems are required to work at higher frequencies and have higher reliability and stability. Therefore, the clock system will directly affect the reliability and stability of the entire system, and as the scale of the FPGA continues to increase, the number of PLLs embedded in the FPGA is also increasing, so how to improve the ...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
IPC IPC(8): G01R31/3177G01R31/3185
CPCG01R31/3177G01R31/318519
Inventor 周芝梅万勇冯晨徐浩韩圣亚黄振王飞
Owner STATE GRID CORP OF CHINA