Preparation method of three-dimensional memory and three-dimensional memory
A memory and three-dimensional technology, applied in the field of semiconductors, can solve problems such as easy short circuits, and achieve the effect of avoiding failure and improving production yield
Active Publication Date: 2020-05-22
YANGTZE MEMORY TECH CO LTD
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Problems solved by technology
[0003] The application provides a method for preparing a three-dimensional memory and a three-dimensional memory, which solves the problem of easy short circuit between the connection hole in the three-dimensional memory and the adjacent gate
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[0040] The following will clearly and completely describe the technical solutions in the embodiments of the application with reference to the drawings in the embodiments of the application. Apparently, the described embodiments are only some of the embodiments of the application, not all of them. Based on the embodiments in this application, all other embodiments obtained by persons of ordinary skill in the art without creative efforts fall within the protection scope of this application.
[0041] see figure 1 , figure 1 It is a partial structural schematic diagram of the existing three-dimensional memory. As more and more layers are stacked in the three-dimensional memory, the problem of abrupt change of stress in the local area of the three-dimensional memory will become prominent, which will lead to misalignment of the connection hole 31 with the gate spacer 14 or the channel hole. And if the alignment deviation between the connection hole 31 and the gate spacer 14 or t...
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The invention provides a preparation method of a three-dimensional memory and the three-dimensional memory. The preparation method comprises the following steps: providing a semiconductor structure, wherein the semiconductor structure comprises a substrate, a stacking structure arranged on the substrate and an etching barrier layer arranged on the stacking structure; the semiconductor structure isprovided with a gate isolation groove penetrating through the etching barrier layer and the stacked structure, and a conductive structure is formed in the gate isolation groove; forming a connectinglayer on one side, back to the stacked structure, of the etching barrier layer; and providing an etching agent to etch the connection layer to form a first connection hole, wherein the first connection hole exposes the conductive structure corresponding to the first connection hole. According to the preparation method provided by the invention, the problem that the connection hole in the three-dimensional memory and the gate close to the connection hole are easily short-circuited is solved.
Description
technical field [0001] The present application relates to the field of semiconductor technology, in particular to a method for preparing a three-dimensional memory and the three-dimensional memory. Background technique [0002] Three-dimensional memory is a memory that realizes the storage and transmission of data in three-dimensional space and greatly improves the storage capacity of storage devices. As the number of stacked layers increases in the existing three-dimensional memory, the problem of sudden change in local stress becomes prominent, resulting in misalignment between the connection hole and the channel hole, which easily leads to a short circuit between the connection hole and the adjacent gate during the process. Contents of the invention [0003] The present application provides a method for preparing a three-dimensional memory and the three-dimensional memory, which solve the problem that a connection hole in the three-dimensional memory is easily short-cir...
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Patent Timeline
Login to View More IPC IPC(8): H01L27/11529H01L27/11531H01L27/11556H01L27/11573H01L27/11582H01L27/11524H01L27/1157
CPCH10B41/42H10B41/41H10B41/35H10B41/27H10B43/40H10B43/35H10B43/27
Inventor 王健舻曾明杨星梅
Owner YANGTZE MEMORY TECH CO LTD