Phase-locked loop circuit

Abstract

A phase-locked loop (PLL) circuit capable of attaining high-speed frequency transition with enhanced reliability. To this end, outputs of a reference signal source (1) and voltage-controlled oscillator (VCO) circuit (3) are frequency-divided by frequency divider circuits (2, 4), respectively. A phase comparator circuit (5) is provided for outputting an error signal indicative of a phase difference between these signals, if any. A window generator circuit (9) is connected for outputting a window signal; where the error signal does not fall within the range of a pulse width of this window signal, a level generator circuit generates a boost voltage having its potential near the control voltage value of the VCO (3) for use in generating of a target frequency. A low-pass filter (LPF) circuit (7) is charged up in responding to receipt of both the output signal of the charge pump circuit (6) and the boost voltage so that the control voltage may rapidly increase in potential at a target value without rising up to any excess values. Whereby, undershoot and overshoot may be eliminated or at least greatly suppressed thus enabling achievement of high-speed frequency transition with increased reliability.

Description

Technical field: [0001] The present invention relates to a phase locked loop circuit (PLL). [0002] Currently, in a PLL circuit usable in a PLL frequency synthesizer in a mobile communication system or the like, several attempts are made to shorten the lock time during start-up and channel switching. Background technique: [0003] A known circuit in the prior art such as Figure 12 As shown in (a), where two low-pass filters (LPF) 123 and 124 with different time constants are provided as an LPF called "loop filter", which averages the production of the charge pump circuit 121 by operation, A control voltage is thereby generated for controlling the frequency of the voltage controlled oscillator (VCO) circuit 122 . By using only one LPF 123 with a shorter time constant during frequency transfer, and after locking, switching it to the remaining LPF 124 with a larger time constant, the circuit serves to shorten the time required to stabilize the loop interval. Further, refer...

AI Technical Summary

Problems solved by technology

Another problem associated with this prior art is that the PLL system may be disturbed at the moment when the comparison frequency used at the start of the handover is switched to the standard frequency for channel switching

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