Packaging substrate preparation method

A technology for packaging substrates and substrates, which is applied in chemical/electrolytic methods to remove conductive materials, printed circuit manufacturing, semiconductor/solid-state device manufacturing, etc., can solve the problems of high cost of packaging substrates, achieve low cost, maintain yield, The effect of improving productivity

Active Publication Date: 2020-06-05
SHENZHEN ZHIJIN ELECTRONICS
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] The object of the present invention is to provide a packaging substrate preparation method, which aims to solve the existing packaging substrate preparation method to prepare packaging substrates with fine lines. question

Method used

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Embodiment Construction

[0033] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without creative efforts fall within the protection scope of the present invention.

[0034] It should be noted that all directional indications (such as up, down, left, right, front, back...) in the embodiments of the present invention are only used to explain the relationship between the components in a certain posture (as shown in the accompanying drawings). Relative positional relationship, movement conditions, etc., if the specific posture changes, the directional indication will also change accordingly.

[0035] It should also be...

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Abstract

The invention is applicable to the technical field of printed circuit boards. The invention discloses a packaging substrate preparation method, which is used for manufacturing a package substrate forchip package. The packaging substrate preparation method comprises: providing a base material which is provided with a copper layer and a metal protective layer covering the copper layer, etching a circuit on the metal protective layer by adopting a laser etching process, and exposing the copper layer; etching along the exposed copper layer to obtain a fine circuit; removing the metal protective layer and exposing the copper layer fine circuit to obtain a semi-finished product; and carrying out copper plating on a semi-finished product, and obtaining a packaging substrate with a finished product fine circuit, etching the metal protection layer through the laser etching process, then etching the exposed copper layer, and obtaining the packaging substrate with the fine circuit with the linewidth / line distance smaller than or equal to 20 / 20 microns. The preparation method is simple, the cost is low, large-batch preparation can be achieved, the production efficiency is improved, and the high yield can be kept.

Description

technical field [0001] The invention relates to the technical field of printed circuit boards, in particular to a method for preparing a packaging substrate. Background technique [0002] With the development of chip miniaturization, the function of the chip is becoming more and more powerful, but the volume is getting smaller and smaller. Therefore, there are higher requirements for the size of the packaging substrate in the chip and the density of wiring. According to the requirements of the circuit in the packaging substrate in the industry, the ordinary design of L / S (line width / line spacing) = 35 / 35um has evolved to the general 25 / 25um and the fine circuit of 20 / 20um or smaller in use . The traditional packaging substrate uses the subtractive method to make the circuit, but limited by the technology itself, its limit fine circuit level is 50 / 50um, and through the additive method or semi-additive method with ultra-thin copper foil, the fine circuit The level can reach ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/48H05K3/02H05K3/06
CPCH01L21/4846H05K3/027H05K3/062H05K2203/107
Inventor 康孝恒蔡克林唐波杨飞李瑞许凯蒋乐元
Owner SHENZHEN ZHIJIN ELECTRONICS
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