Multiplier, data processing method, chip and electronic equipment

A multiplier and data technology, applied in the computer field, can solve the problem of multiplier multi-power consumption, and achieve the effect of reducing power consumption

Active Publication Date: 2020-06-09
SHANGHAI CAMBRICON INFORMATION TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] However, after the traditional technology performs the sign bit extension to eliminate the partial product and eliminates the inversion plus one operation, when using the Wallace tree for partial product compressio

Method used

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  • Multiplier, data processing method, chip and electronic equipment
  • Multiplier, data processing method, chip and electronic equipment
  • Multiplier, data processing method, chip and electronic equipment

Examples

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Embodiment Construction

[0048] In order to make the purpose, technical solution and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present application, and are not intended to limit the present application.

[0049]The multiplier provided by this application can be applied to AI chips, field programmable gate array FPGA (Field-Programmable Gate Array, FPGA) chips, or other hardware circuit devices for multiplication processing. The specific structural diagram is as follows figure 1 shown.

[0050] figure 1 A specific structural schematic diagram of a multiplier provided for an embodiment, such as figure 1 As shown, the multiplier includes: an encoding circuit 11, a deformed Wallace tree group circuit 12 and an accumulation circuit 13, the output end of the encoding circuit 11...

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Abstract

The invention provides a multiplier, a data processing method, a chip and electronic equipment. The multiplier comprises: a coding circuit, a malformed Wallace tree group circuit and an accumulation circuit, the output end of the encoding circuit is connected with the input end of the malformed Wallace tree group circuit, the output end of the malformed Wallace tree group circuit is connected withthe input end of the accumulation circuit, and the multiplier can remove and process a numerical value of 0 on the premise of completely ensuring the operation accuracy of the multiplier, so that thepower consumption of the multiplier is effectively reduced.

Description

technical field [0001] The invention relates to the technical field of computers, in particular to a multiplier, a data processing method, a chip and electronic equipment. Background technique [0002] With the continuous development of digital electronic technology, the rapid development of various artificial intelligence (AI) chips has higher and higher requirements for high-performance digital multipliers. The neural network algorithm is one of the algorithms widely used in smart chips, and the multiplication operation through the multiplier is a common operation in the neural network algorithm. [0003] At present, the multiplier uses the Booth algorithm to obtain the partial product, compresses the partial product through the Wallace tree, and uses an adder to accumulate the compressed result and output the final result. [0004] However, after the traditional technology performs the sign bit extension to eliminate the partial product and eliminates the negation plus o...

Claims

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Application Information

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IPC IPC(8): G06F7/527G06N3/063
CPCG06F7/527G06N3/063Y02D10/00
Inventor 不公告发明人
Owner SHANGHAI CAMBRICON INFORMATION TECH CO LTD
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