Redundant system design of information processing platform

An information processing platform and redundant system technology, applied in the field of information processing platform redundant system design, can solve the problems of insufficient redundancy depth of multi-level redundant design technology, affecting the independence of system design, and reducing system reliability. Improve the depth and stability of redundancy, improve fault location and analysis capabilities, and enhance the effect of flexibility

Pending Publication Date: 2020-06-09
JIANGSU HUACHUNG MICROSYSTEM CO LTD +1
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Problems solved by technology

[0003] The traditional multi-level redundancy design technology has insufficient redundancy depth, and the management at the module level and platform level needs to be strengthened, which leads to a high degree of coupling

Method used

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  • Redundant system design of information processing platform
  • Redundant system design of information processing platform
  • Redundant system design of information processing platform

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Embodiment Construction

[0038] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

[0039] see figure 1 , figure 2 , image 3 , Figure 4 , Figure 5 and Image 6 , the present invention provides a technical solution:

[0040] Including multi-layer reset and multi-level redundancy functions; multi-layer reset includes: module-level reset and subrack-level reset; multi-level redundancy: including management redundancy, SRIO switching redundancy, network redundancy and bit reporting redundancy , the related software includes 4 main funct...

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Abstract

The invention discloses a redundant system design of an information processing platform. A multistage redundancy scheme of the whole system is designed, comprising a multi-layer reset function and a multi-stage redundancy function. Multi-stage redundancy includes managing redundancy, SRIO switching redundancy, network redundancy and bit reporting redundancy. Single-module fault monitoring and recovery and system fault monitoring and recovery are involved. Omni-directional redundancy is realized, and the redundancy depth of the whole system is improved. Intelligent management of the module level and the platform level is achieved, system reconstruction is improved to the system level from the chip level, the coupling degree between modules is reduced, the independence of system design is guaranteed, the reliability of the system is greatly improved, design guarantee is provided for steady operation of an application system, and the operation risk of the system is effectively shared.

Description

technical field [0001] The invention relates to the technical field of redundant systems, in particular to the design of redundant systems for information processing platforms. Background technique [0002] The information processing platform is built with Huarui No. 2. The system is designed based on the multi-core processor of Huarui No. 2. When working, multiple Huarui No. 2 processors obtain information, process data, and calculate results through high-speed communication links, and output the results to post-processing. In various application scenarios, the HuaRay No. 2 information processing platform does not allow the entire system to crash or be paralyzed due to an abnormal state or failure of a certain processor, a certain chip, or a certain communication link. Therefore, in the system design of Huarui No. 2 platform, it is necessary to adopt multi-level redundancy design technology to improve the stability and reliability of system operation. Hua Rui No. 2 platfo...

Claims

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Application Information

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IPC IPC(8): H04L12/24H04L1/22
CPCH04L41/0677H04L1/22H04L41/0663
Inventor 朱秉颖许光政
Owner JIANGSU HUACHUNG MICROSYSTEM CO LTD
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