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Data transmission method, device and system

A technology of a data transmission device and a data transmission method, which is applied in the field of communication and can solve problems such as inability to meet data transmission application scenarios

Active Publication Date: 2020-06-23
YUSUR TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] However, the current mainstream TOE solutions can only support a network transmission rate of up to 10Ghz, which cannot meet some high-demand data transmission application scenarios.

Method used

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  • Data transmission method, device and system
  • Data transmission method, device and system
  • Data transmission method, device and system

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0069] Embodiment 1: When the network connection is established, the PC sends an instruction to update the IP record table to the PC interactive logic control unit through PCIE, and the instruction sent includes: the IP address and port number of the target terminal, and each time an IP address and port number are updated, The IP record table module notifies the data transmission control module to generate an ARP signal, and the TCP / IP packet transmission control module in the logic control unit of the TCP / IP protocol stack arrives at the TCP / IP encoding module to generate an ARP request packet, and the MAC transmission module passes through 40G The optical transceiver module sends to the target IP address; when receiving the ARP response packet, the MAC receiving module receives the ARP response packet from the 40G optical transceiver module and submits it to the TCP / IP decoding module for analysis, and the parsed ARP information is transmitted through the TCP / IP packet The co...

Embodiment 2

[0070] Embodiment two: when sending TCP / IP packet, PC sends the address of the data sent in DDR and the length (in byte) of packet, destination IP address and port number to PC interactive logic control unit, The PC interactive logic control unit sends these information to the data sending control module, and the data sending control module hands over the IP address and port number to the IP record table module to judge whether the IP address and port number are legal, if legal, the data sending control module Send the information of sending data to the TCP / IP packet transmission control module in the logic control unit of the TCP / IP protocol stack, and then the TCP / IP packet transmission control module reads the corresponding data from DDR according to the DDR data address and data packet length information therein The data will be encoded and packaged by the TCP / IP encoding module, and then sent by the MAC sending module through the 40G optical transceiver module, thus comple...

Embodiment 3

[0071] Embodiment three: when receiving TCP / IP data packets, the MAC receiving module receives TCP / IP packets from the 40G optical transceiver module and submits them to the TCP / IP decoding module for parsing and performing packet header verification and data correctness verification. If the verification is passed, the DDR address to store the data is calculated, and then the data is sent to the storage control module of the transceiver logic control unit, and the data is stored in the DDR; at the same time, the DDR address, the length of the data packet, the sender's IP address and The port number is sent to the data receiving control module of the transceiver logic control unit, and the receiving control module sends the IP address and port number to the IP record table module for verification. If it is legal, the above information is cached in FIFO, and the PC is waiting for the PC to interact with the logic. After the control unit sends and receives the instruction, it send...

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PUM

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Abstract

The invention discloses a data transmission method, device and system. The device is integrated on an FPGA. The apparatus comprises: an apparatus body; the system comprises a protocol stack logic control unit, a transmit-receive control logic unit, a data interaction control unit and an over-ten-gigabit optical transmit-receive unit used for receiving / sending data. The protocol stack logic controlunit is used for acquiring to-be-sent data, encoding the to-be-sent data according to a TCP / IP protocol, sending the encoded to-be-sent data through the over-ten-gigabit optical transceiver unit, decoding the to-be-received data received through the over-ten-gigabit optical transceiver unit according to the TCP / IP protocol, and sending the decoded to-be-received data to the transceiver control logic unit; transceiving control logic unit, the verification module is used for receiving the to-be-sent data information from the CPU and carrying out validity verification on the to-be-sent data information; and when the data is legal, sending the to-be-sent data information to the protocol stack logic control unit, and storing the decoded to-be-received data to an external memory according to verification of the legality of the decoded to-be-received data from the protocol stack logic control unit.

Description

technical field [0001] The present invention relates to the communication field, in particular to a data transmission method, device and system. Background technique [0002] As an important Internet (network) protocol, the TCP / IP (Transmission Control Protocol / Internet Protocol, Transmission Control Protocol / Internet Protocol) protocol has always been in the basic position of network communication. In a traditional system composed of common network cards, the analysis of the TCP / IP protocol is completed by the CPU (central processing unit, central processing unit), which requires a high CPU resource of the server. Specifically, when network applications send and receive data, they often have to copy multiple copies of the same data. In this case, due to the continuous data exchange between the network interface buffer and the application memory, these additional burdens are greatly increased. The processing efficiency of the main CPU is reduced, and the average waiting tim...

Claims

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Application Information

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IPC IPC(8): H04L29/06H04L29/12H04L1/18H04B10/516
CPCH04B10/516H04L1/1816H04L61/103H04L63/12H04L69/161
Inventor 鄢贵海卢文岩石阳肖凡
Owner YUSUR TECH CO LTD
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