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Hierarchical digital circuit reliability verification method

A digital circuit and verification method technology, applied in the direction of electrical digital data processing, CAD circuit design, special data processing applications, etc., can solve problems such as practical difficulties and a sharp increase in the amount of calculation, and achieve reliability verification design, fast reliability Verification, the effect of saving time for reliability verification

Pending Publication Date: 2020-08-18
DALIAN UNIV OF TECH
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Problems solved by technology

[0005] The present invention mainly solves technical problems such as direct simulation of transistor-level degradation characteristics in the prior art, which will lead to a sharp increase in the amount of calculation, and is difficult in reality, and proposes a hierarchical digital circuit reliability verification method to save reliability of large-scale digital circuits Verification time, improve verification efficiency

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  • Hierarchical digital circuit reliability verification method
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  • Hierarchical digital circuit reliability verification method

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Embodiment Construction

[0031] In order to make the technical problems solved by the present invention, the technical solutions adopted and the technical effects achieved clearer, the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present invention, but not to limit the present invention. In addition, it should be noted that, for the convenience of description, only parts related to the present invention are shown in the drawings but not all content.

[0032] figure 1 It is an implementation flowchart of the hierarchical digital circuit reliability verification method provided by the embodiment of the present invention. Such as figure 1 As shown, the hierarchical digital circuit reliability verification method provided by the embodiment of the present invention includes:

[0033] Step 100, in the BSIM 3v3 model, use the calcul...

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Abstract

The invention relates to the field of circuit reliability verification, and provides a hierarchical digital circuit reliability verification method. The method comprises the steps that in a BSIM 3v3 model, a new BSIM 3v3 model capable of evaluating the performance change condition of a mosfet transistor is formed through a calculation formula of threshold voltage drift deltaVth of the mosfet transistor affected by HCI, NBTI and TDDB effects, calling a new BSIM 3v3 model by utilizing the SPICE simulator to simulate a circuit only containing one mosfet transistor, so as to generate a degraded mosfet transistor model file, extracting a degraded digital cell library through a cell library characterization tool on the basis of the degraded mosfet transistor model file, and finally, analyzing the digital circuit based on the degraded digital unit library to predict the performance degradation of the large-scale digital circuit. The large-scale digital circuit reliability verification time can be saved.

Description

technical field [0001] The invention relates to the field of circuit reliability verification, in particular to a layered digital circuit reliability verification method. Background technique [0002] On the one hand, the development of integrated circuits is to develop towards a larger scale of integration, and continuously improve the performance-price ratio of integrated circuits and systems, which improves the performance of devices and circuits, reduces the production cost of unit circuits, and improves system performance and price. The most effective way is to continuously reduce the feature size and improve integration. On the other hand, with the rapid development of the reliability of integrated circuits in the direction of miniaturization, high integration, and multi-functionality with the application of aviation and aerospace technology and complex electronic equipment such as military and civilian use, in some fields people are more concerned about ultra-large-sc...

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F30/33G06F119/02
CPCG06F30/33G06F2119/02
Inventor 常玉春刘岩马艳华娄珊珊杨刚宋辰昱
Owner DALIAN UNIV OF TECH