Algorithm for optimizing redundant weight of capacitor array in SAR ADC

Abstract

The invention discloses an algorithm for optimizing the redundant weight of a capacitor array in an SAR ADC, and the algorithm comprises the following steps: S1, selecting the value section of CX, CL,CB and CM according to the bit number n of a designed ADC; S2, defining a judgment condition 1: 2 < = WL-2 * W1M < = 6; S3, defining a judgment condition 2: W = 2n; and S4, scanning the CX, the CL, the CB and the CM in the value section according to the judgment condition 1 and the defined judgment condition 2 to obtain values of the CX, the CL, the CB and the CM. The algorithm can be applied tothe design of a chip needing a high-speed and high-precision successive approximation analog-to-digital converter. According to the redundant capacitor array optimized by the algorithm, the requirements for capacitance matching and parasitism of adjacent bits in the DAC can be lowered, the requirements for the speed of the comparator are lowered, and enough redundant space is provided for comparison each time, so that static nonlinear errors caused by capacitance mismatching and dynamic errors caused by the speed of the comparator are eliminated. The method has unique advantages in the field of design of high-speed and high-precision successive approximation analog-to-digital converters.

Description

technical field [0001] The invention relates to the technical field of chip design of a high-speed and high-precision successive approximation analog-to-digital converter, in particular to an algorithm for optimizing the redundancy weight of a capacitor array in a SAR ADC. Background technique [0002] Description: This algorithm can be used to optimize the redundancy weight of the binary capacitor array in the n-bit segmented charge redistribution SAR ADC. The following uses a 12-bit segmented charge redistribution SAR ADC as an example for illustration. [0003] In the traditional 12bit segmented charge redistribution SAR ADC design, the DAC composed of a binary weighted capacitor array, as shown in the attached figure 1 As shown, CB is a coupling capacitor, C0 is a redundant capacitor, and C1-C12 are binary weighted capacitors. attached figure 1 The weight coefficient of each bit in can be expressed by formula (1): [0004] [0005] For attached figure 1 As shown i...

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Problems solved by technology

but with figure 2 In the 12-bit binary capacitor array with redundant weights shown in , there is a defect in the design of redundant bits, that is, the distribution of capacitor weights is unreasonable, resulting in an unreasonable error tolerance space: as attached figure 2 As shown, the redundancy of some capacitors is too large (such as C14, the redundancy weight R14=666, and the redundancy utilization is not enough), resulting in waste of redundant space; while the redundant space of another part of the capacitor is too small (such as C7 and C8, The redundancy is 1), or even no redundancy (such as C4, redundancy R4 = 0, when the weight of the conversion error introduced by the bit due to the mismatch of the capacitor or the incomplete establishment of the comparator is greater than 0, the DAC will not be able to correct it), lead to uncorrectable error

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